Datasheet

SCL
SDA
t
(LOW)
t
R
t
F
t
(HDSTA)
t
(HDSTA)
t
(HDDAT)
t
(BUF)
t
(SUDAT)
t
(HIGH)
t
(SUSTA)
t
(SUSTO)
P S S P
TMP421
TMP422
TMP423
SBOS398C –JULY 2007–REVISED MAY 2012 www.ti.com
TIMING DIAGRAMS Data Transfer: The number of data bytes transferred
between a START and a STOP condition is not
The TMP421/22/23 are two-wire and SMBus-
limited and is determined by the master device. The
compatible. Figure 16 to Figure 19 describe the
receiver acknowledges data transfer.
timing for various operations on the TMP421/22/23.
Parameters for Figure 16 are defined in Table 11. Acknowledge: Each receiving device, when
Bus definitions are: addressed, is obliged to generate an Acknowledge
bit. A device that acknowledges must pull down the
Bus Idle: Both SDA and SCL lines remain high.
SDA line during the Acknowledge clock pulse in such
a way that the SDA line is stable low during the high
Start Data Transfer: A change in the state of the
period of the Acknowledge clock pulse. Setup and
SDA line, from high to low, while the SCL line is high,
hold times must be taken into account. On a master
defines a START condition. Each data transfer
receive, data transfer termination can be signaled by
initiates with a START condition. Denoted as S in
the master generating a Not-Acknowledge on the last
Figure 16.
byte that has been transmitted by the slave.
Stop Data Transfer: A change in the state of the
SDA line from low to high while the SCL line is high
defines a STOP condition. Each data transfer
terminates with a repeated START or STOP
condition. Denoted as P in Figure 16.
Figure 16. Two-Wire Timing Diagram
Table 11. Timing Characteristics for Figure 16
FAST MODE HIGH-SPEED MODE
PARAMETER MIN MAX MIN MAX UNIT
SCL Operating Frequency f
(SCL)
0.001 0.4 0.001 3.4 MHz
Bus Free Time Between STOP and START Condition t
(BUF)
600 160 ns
Hold time after repeated START condition. After this period, the first clock
t
(HDSTA)
100 100 ns
is generated.
Repeated START Condition Setup Time t
(SUSTA)
100 100 ns
STOP Condition Setup Time t
(SUSTO)
100 100 ns
Data Hold Time t
(HDDAT)
0
(1)
0
(2)
ns
Data Setup Time t
(SUDAT)
100 10 ns
SCL Clock LOW Period t
(LOW)
1300 160 ns
SCL Clock HIGH Period t
(HIGH)
600 60 ns
Clock/Data Fall Time t
F
300 160 ns
Clock/Data Rise Time t
R
300 160
ns
for SCL ≤ 100kHz t
R
1000
(1) For cases with fall time of SCL less than 20ns and/or the rise or fall time of SDA less than 20ns, the hold time should be greater than
20ns.
(2) For cases with a fall time of SCL less than 10ns and/or the rise or fall time of SDA less than 10ns, the hold time should be greater than
10ns.
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