Datasheet
TMP411-Q1
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SBOS527F –DECEMBER 2010–REVISED NOVEMBER 2013
TIMING DIAGRAMS
Data Transfer: The number of data bytes transferred
between a START and a STOP condition is not
The TMP411-Q1 is two-wire and SMBus-compatible.
limited and is determined by the master device. The
Figure 13 to Figure 17 describe the various
receiver acknowledges the transfer of data.
operations on the TMP411-Q1. Bus definitions are
given as follows. Parameters for Figure 13 are
Acknowledge: Each receiving device, when
defined in Table 13.
addressed, is obliged to generate an Acknowledge
bit. A device that acknowledges must pull down the
Bus Idle: Both SDA and SCL lines remain high.
SDA line during the Acknowledge clock pulse in such
Start Data Transfer: A change in the state of the a way that the SDA line is stable low during the high
SDA line, from high to low, while the SCL line is high, period of the Acknowledge clock pulse. Setup and
defines a START condition. Each data transfer is hold times must be taken into account. On a master
initiated with a START condition. receive, data transfer termination can be signaled by
the master generating a Not-Acknowledge on the last
Stop Data Transfer: A change in the state of the
byte that has been transmitted by the slave.
SDA line from low to high while the SCL line is high
defines a STOP condition. Each data transfer
terminates with a STOP or a repeated START
condition.
Figure 13. Two-Wire Timing Diagram
Table 13. Timing Diagram Definitions for Figure 13
PARAMETER FAST MODE HIGH-SPEED MODE UNITS
MIN MAX MIN MAX
f
(SCL)
SCL operating frequency 0.001 0.4 0.001 3.4 MHz
t
(BUF)
Bus free time between STOP and 600 160
ns
START conditions
t
(HDSTA)
Hold time after repeated START 100 100
condition. After this period, the first ns
clock is generated.
t
(SUSTA)
Repeated START condition setup time 100 100 ns
t
(SUSTO)
STOP condition setup time 100 100 ns
t
(HDDAT)
Data hold time 0
(1)
0
(2)
ns
t
(SUDAT)
Data setup time 100 10 ns
t
(LOW)
SCL clock LOW period 1300 160 ns
t
(HIGH)
SCL clock HIGH period 600 60 ns
t
f
Clock and data fall time 300 160 ns
t
r
Clock and data rise time 300 160 ns
t
r
for SCLK ≤ 100 kHz 1000 ns
(1) For cases with fall time of SCL less than 20 ns and/or the rise time or fall time of SDA less than 20 ns, the hold time should be greater
than 20 ns.
(2) For cases with fall time of SCL less than 10 ns and/or the rise or fall time of SDA less than 10 ns, the hold time should be greater than
10 ns.
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