Datasheet

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SBOS383C − DECEMBER 2006 − REVISED MAY 2008
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19
Frame1Two−Wire Slave Address Byte Frame 2 Pointer Register Byte
1
Start By
Master
ACK By
TMP411A
ACK By
TMP411A
Frame3Two−WireSlaveAddressByte Frame4DataByte1ReadRegister
Start By
Master
ACK By
TMP411A
ACK By
Master
From
TMP411A
191 9
191 9
SDA
SCL
001 R/W
P7 P6 P5 P4 P3 P2 P1 P0
SDA
(Continued)
SCL
(Continued)
SDA
(Continued)
SCL
(Continued)
1001
100
(1)
100
(1)
R/W D7 D6 D5 D4 D3 D2 D1 D0
Frame 5 Data Byte 2 Read Register
Stop By
Master
NACK By
Master
(2)
From
TMP411A
19
D7 D6 D5 D4 D3 D2 D1 D0
(1) Slave address 1001100 (TMP411A) shown. Slave address changes for TMP411B and TMP411C. See Ordering Information table for more details.
(2) Master should leave SDA high to terminate a two−byte read operation.
NOTES:
Figure 16. Two-Wire Timing Diagram for Two-Byte Read Format
Frame 1 SMBus ALERT Response Address Byte Frame 2 Slave Address Byte
Start By
Master
ACK By
TMP411A
From
TMP411A
NACK By
Master
Stop By
Master
1919
SDA
SCL
ALERT
0001100R/W 1001100
(1)
Status
NOTE (1): Slave address 1001100 (TMP411A) shown. Slave address changes for TMP411B and TMP411C. See Ordering Information table for more details.
Figure 17. Timing Diagram for SMBus ALERT