Datasheet

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SBOS383C − DECEMBER 2006 − REVISED MAY 2008
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16
SERIAL INTERFACE
The TMP411 operates only as a slave device on either the
Two-Wire bus or the SMBus. Connections to either bus are
made via the open-drain I/O lines, SDA and SCL. The SDA
and SCL pins feature integrated spike suppression filters
and Schmitt triggers to minimize the effects of input spikes
and bus noise. The TMP411 supports the transmission
protocol for fast (1kHz to 400kHz) and high-speed (1kHz
to 3.4MHz) modes. All data bytes are transmitted MSB
first.
SERIAL BUS ADDRESS
To communicate with the TMP411, the master must first
address slave devices via a slave address byte. The slave
address byte consists of seven address bits, and a
direction bit indicating the intent of executing a read or
write operation.
The address of the TMP411A is 4Ch (1001100b). The
address of the TMP411B is 4Dh (1001101b). The address
of the TMP411C is 4Eh (1001110b).
READ/WRITE OPERATIONS
Accessing a particular register on the TMP411 is
accomplished by writing the appropriate value to the
Pointer Register. The value for the Pointer Register is the
first byte transferred after the slave address byte with the
R/W
bit low. Every write operation to the TMP411 requires
a value for the Pointer Register (see Figure 14).
When reading from the TMP411, the last value stored in
the Pointer Register by a write operation is used to
determine which register is read by a read operation. To
change the register pointer for a read operation, a new
value must be written to the Pointer Register. This
transaction is accomplished by issuing a slave address
byte with the R/W
bit low, followed by the Pointer Register
byte. No additional data are required. The master can then
generate a START condition and send the slave address
byte with the R/W
bit high to initiate the read command.
See Figure 15 for details of this sequence. If repeated
reads from the same register are desired, it is not
necessary to continually send the Pointer Register bytes,
because the TMP411 retains the Pointer Register value
until it is changed by the next write operation. Note that
register bytes are sent MSB first, followed by the LSB.
Table 11. THERM Hysteresis Register Format
THERM HYSTERESIS REGISTER (Read = 21h, Write = 21h, POR = 0Ah)
BIT #
D7
D6
D5
D4
D3
D2
D1
D0
BIT #
D7
D6
D5
D4
D3
D2
D1
D0
BIT NAME TH11 TH10 TH9 TH8 TH7 TH6 TH5 TH4
POR VALUE 0 0 0 0 1 0 1 0