Datasheet

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SBOS371A − AUGUST 2006 − REVISED OCTOBER 2007
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17
Frame 1 Two−Wire Slave Address Byte Frame 2 Pointer Register Byte
1
Start By
Master
ACK By
TMP401
ACK By
TMP401
Frame3Two−WireSlaveAddressByte Frame4DataByte1ReadRegister
Start By
Master
ACK By
TMP401
ACK By
Master
From
TMP401
191 9
191 9
SDA
SCL
0 0 1 R/W P7 P6 P5 P4 P3 P2 P1 P0
…
…
…
…
SDA
(Continued)
SCL
(Continued)
SDA
(Continued)
SCL
(Continued)
1001
100
100
R/W
D7 D6 D5 D4 D3 D2 D1 D0
Frame5DataByte2ReadRegister
Stop By
Master
ACK By
Master
From
TMP401
19
D7 D6 D5 D4 D3 D2 D1 D0
Figure 15. Two-Wire Timing Diagram for Read Word Format
Frame 1 SMBus ALERT Response Address Byte Frame 2 Slave Address Byte
Start By
Master
ACK By
TMP401
From
TMP401
NACK By
Master
Stop By
Master
191 9
SDA
SCL
ALERT
0001100R/W 1001100
Status
Figure 16. Timing Diagram for SMBus ALERT