Datasheet
Frame1Two-WireSlaveAddressByte Frame2PointerRegisterByte
1
StartBy
Master
ACKBy
TMP112
ACKBy
TMP112
Frame3Two-WireSlaveAddressByte Frame4DataByte1ReadRegister
StartBy
Master
ACKBy
TMP112
ACKBy
Master
(2)
From
TMP112
1 9 1
9
1 9 1
9
SDA
SCL
0 0 1 R/W
0 0 0 0 0 0 P1 P0
¼
¼
¼
SDA
(Continued)
SCL
(Continued)
SDA
(Continued)
SCL
(Continued)
1 0 0 1
0
A1
(1)
A0
(1)
0
A1
(1)
A0
(1)
R/W D7 D6 D5 D4 D3 D2 D1 D0
Frame5DataByte2ReadRegister
StopBy
Master
ACKBy
Master
(3)
From
TMP112
1
9
D7 D6 D5 D4 D3 D2 D1 D0
StopBy
Master
NOTE: (1)ThevaluesofA0andA1aredeterminedbytheADD0pin.
(2)MastershouldleaveSDAhightoterminateasingle-bytereadoperation.
(3)MastershouldleaveSDAhightoterminateatwo-bytereadoperation.
NOTE:(1)ThevaluesofA0andA1aredeterminedbytheADD0pin.
Frame1SMBusALERTResponseAddressByte Frame2SlaveAddressFromTMP112
StartBy
Master
ACKBy
TMP112
From
TMP112
NACKBy
Master
StopBy
Master
1 9 1
9
SDA
SCL
ALERT
0 0 0 1 1 0 0 R/
W 1 0 0 1 A1 A0
Status
TMP112
www.ti.com
......................................................................................................................................................... SBOS473B – MARCH 2009 – REVISED JUNE 2009
Figure 17. Two-Wire Timing Diagram for Read Word Format
Figure 18. Timing Diagram for SMBus ALERT
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): TMP112