Datasheet
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SLLS672A − OCTOBER 2005 − REVISED JANUARY 2006
www.ti.com
11
Frame1Two−WireSlaveAddressByte
Frame 2 Pointer Register Byte
Frame 4 Data Byte 2
1
Start By
Master
ACK By
TMP106
ACK By
TMP106
ACK By
TMP106
Stop By
Master
191
1
D7 D6 D5 D4 D3 D2 D1 D0
9
Frame3DataByte1
ACK By
TMP106
1
D7
SDA
(Continued)
SCL
(Continued)
D6 D5 D4 D3 D2 D1 D0
9
9
SDA
SCL
0 0 1 0 0 A0 R/W 0 0 0 0 0 0 P1 P0
…
…
Figure 5. Two-Wire Timing Diagram for TMP106 Write Word Format
Frame 1 Two−Wire Slave Address Byte Frame 2 Pointer Register Byte
1
Start By
Master
ACK By
TMP106
ACK By
TMP106
Frame3Two−WireSlaveAddressByte Frame4DataByte1ReadRegister
Start By
Master
ACK By
TMP106
ACK By
Master
From
TMP106
191 9
191 9
SDA
SCL
00 R/W 000000P1P0
…
…
…
…
SDA
(Continued)
SCL
(Continued)
SDA
(Continued)
SCL
(Continued)
1001
00A0
00A0
R/W
D7 D6 D5 D4 D3 D2 D1 D0
Frame5DataByte2ReadRegister
Stop By
Master
ACK By
Master
From
TMP106
19
D7 D6 D5 D4 D3 D2 D1 D0
Figure 6. Two-Wire Timing Diagram for Read Word Format