Datasheet

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FEATURES

D TWO ADDRESSES

D DIGITAL OUTPUT: Two-Wire Serial Interface

D RESOLUTION: 9- to 12-Bits, User-Selectable

D ACCURACY:

±2.0°C (max) from −25°C to +85°C

±3.0°C (max) from −40°C to +125°C

D LOW QUIESCENT CURRENT:

50µA, 0.1µA Standby

D NO POWER-UP SEQUENCE REQUIRED, I

PULLUPS CAN BE ENABLED PRIOR TO V+

APPLICATIONS

D NOTEBOOK COMPUTERS

D COMPUTER PERIPHERAL THERMAL

PROTECTION

D CELL PHONES

D BATTERY MANAGEMENT

D THERMOSTAT CONTROLS

D ENVIRONMENTAL MONITORING AND HVAC

SDA

SCL

V+

GND

ALERT

YZC LEAD−FREE

2 X 3 ARRAY

(TOP VIEW)

Note: Pin A1 is marked with a for Pb−free (YZC)

1,65 mm

1,50 mm

1,15 mm

1,00 mm

(Bump Side Down)

‘’

DESCRIPTION

The TMP106 is a two-wire, serial output temperature

sensor available in a WCSP package. Requiring no

external components, the TMP106 is capable of reading

temperatures with a resolution of 0.0625°C.

The TMP106 features a Two-Wire interface that is

SMBus-compatible, with the TMP106 allowing up to two

devices on one bus. The TMP106 also features an SMBus

Alert function.

The TMP106 is ideal for extended temperature

measurement in a variety of communication, computer,

consumer, environmental, industrial, and instrumentation

applications.

The TMP106 is specified for operation over a temperature

range of −40°C to +125°C.

Diode

Te mp .

Sensor

∆Σ

A/D

Converter

OSC

Control

Logic

Serial

Interface

Config.

and Temp.

TMP106

Temperature

V+

SDA

GND

SCL

B1 B2

ALERT

TMP106

SLLS672A − OCTOBER 2005 − REVISED JANUARY 2006

Digital Temperature Sensor

with Two-Wire Interface

Chip-Scale

Package

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Summary of content (16 pages)

PAGE 1
TMP106 Chip-Scale Package SLLS672A − OCTOBER 2005 − REVISED JANUARY 2006 Digital Temperature Sensor with Two-Wire Interface FEATURES D D D D DESCRIPTION TWO ADDRESSES DIGITAL OUTPUT: Two-Wire Serial Interface RESOLUTION: 9- to 12-Bits, User-Selectable ACCURACY: ±2.0°C (max) from −25°C to +85°C ±3.0°C (max) from −40°C to +125°C D LOW QUIESCENT CURRENT: 50µA, 0.
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" #$% www.ti.com SLLS672A − OCTOBER 2005 − REVISED JANUARY 2006 ABSOLUTE MAXIMUM RATINGS(1) Power Supply, V+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0V Input Voltage(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5V to 7.0V Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA Operating Temperature Range . . . . . . . . . . . . . . . −55°C to +127°C Storage Temperature Range . . . . . . . . . . . . . . . . .
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" #$% www.ti.com SLLS672A − OCTOBER 2005 − REVISED JANUARY 2006 ELECTRICAL CHARACTERISTICS At TA = −40°C to +125°C, and V+ = 2.7V to 5.5V, unless otherwise noted. TMP106 PARAMETER CONDITION MIN TYP MAX UNITS TEMPERATURE INPUT +125 °C −25°C to +85°C ±0.5 ±2.0 °C −40°C to +125°C ±1.0 ±3.0 °C 0.2 ±0.5 °C/V Range −40 Accuracy (Temperature Error) vs Supply Resolution(1) Selectable 0.0625 °C 3 pF DIGITAL INPUT/OUTPUT Input Capacitance Input Logic Levels: VIH VIL 2.1 6.0 −0.5 0.
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" #$% www.ti.com SLLS672A − OCTOBER 2005 − REVISED JANUARY 2006 TYPICAL CHARACTERISTICS At TA = +25°C and V+ = 5.0V, unless otherwise noted. SHUTDOWN CURRENT vs TEMPERATURE QUIESCENT CURRENT vs TEMPERATURE 60 1.0 V+ = 2.8V 0.9 V+ = 5V 50 0.8 0.7 0.6 ISD (µA) IQ (µA) 40 V+ = 2.7V 30 0.5 0.4 0.3 20 0.2 0.1 10 0.0 Serial Bus Inactive −0.
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" #$% www.ti.com SLLS672A − OCTOBER 2005 − REVISED JANUARY 2006 APPLICATIONS INFORMATION The TMP106 is a digital temperature sensor that is optimal for thermal management and thermal protection applications. The TMP106 is Two-Wire and SMBus interface-compatible, and is specified over a temperature range of −40°C to +125°C. Pointer Register Temperature Register The TMP106 requires no external components for operation except for pull-up resistors on SCL, SDA, and ALERT, although a 0.
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" #$% www.ti.com SLLS672A − OCTOBER 2005 − REVISED JANUARY 2006 POLARITY (POL) TEMPERATURE (°C) DIGITAL OUTPUT (BINARY) HEX 128 0111 1111 1111 7FF 127.9375 0111 1111 1111 7FF 100 0110 0100 0000 640 80 0101 0000 0000 500 75 0100 1011 0000 4B0 50 0011 0010 0000 320 25 0001 1001 0000 190 0.25 0000 0000 0100 004 0 0000 0000 0000 000 −0.
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" #$% www.ti.com SLLS672A − OCTOBER 2005 − REVISED JANUARY 2006 CONVERTER RESOLUTION (R1/R0) The Converter Resolution bits control the resolution of the internal analog-to-digital (A/D) converter. This control allows the user to maximize efficiency by programming for higher resolution or faster conversion time. Table 8 identifies the resolution bits and the relationship between resolution and conversion time. R1 R0 RESOLUTION CONVERSION TIME (typical) 0 0 9 Bits (0.5°C) 27.5ms 0 1 10 Bits (0.
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" #$% www.ti.com SLLS672A − OCTOBER 2005 − REVISED JANUARY 2006 SERIAL BUS ADDRESS To communicate with the TMP106, the master must first address slave devices via a slave address byte. The slave address byte consists of seven address bits, and a direction bit indicating the intent of executing a read or write operation. The TMP106 features one address pin allowing up to two devices to be connected per bus. Pin logic levels are described in Table 11.
PAGE 9
" #$% www.ti.com SLLS672A − OCTOBER 2005 − REVISED JANUARY 2006 SLAVE MODE OPERATIONS The TMP106 can operate as a slave receiver or slave transmitter. Slave Receiver Mode: The first byte transmitted by the master is the slave address, with the R/W bit LOW. The TMP106 then acknowledges reception of a valid address. The next byte transmitted by the master is the Pointer Register. The TMP106 then acknowledges reception of the Pointer Register byte.
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" #$% www.ti.com SLLS672A − OCTOBER 2005 − REVISED JANUARY 2006 TIMING DIAGRAMS Data Transfer: The number of data bytes transferred between a START and a STOP condition is not limited and is determined by the master device. The receiver acknowledges the transfer of data. The TMP106 is Two-Wire- and SMBus-compatible. Figure 4 to Figure 7 describe the various operations on the TMP106. Bus definitions are given below. Parameters for Figure 4 are defined in Table 12.
PAGE 11
" #$% www.ti.com SLLS672A − OCTOBER 2005 − REVISED JANUARY 2006 1 9 1 9 … SCL 1 SDA 0 0 1 0 0 A0 R/W Start By Master 0 0 0 0 0 0 P1 … P0 ACK By TMP106 ACK By TMP106 Frame 2 Pointer Register Byte Frame 1 Two−Wire Slave Address Byte 1 1 9 9 SCL (Continued) SDA (Continued) D7 D6 D5 D4 D3 D2 D1 D7 D0 D6 D5 D4 D3 D2 D1 D0 ACK By TMP106 ACK By TMP106 Stop By Master Frame 4 Data Byte 2 Frame 3 Data Byte 1 Figure 5.
PAGE 12
" #$% www.ti.com SLLS672A − OCTOBER 2005 − REVISED JANUARY 2006 ALERT 1 9 1 9 SCL SDA Start By Master 0 0 0 1 1 0 0 R/W 1 0 0 1 0 ACK By TMP106 Frame 1 SMBus ALERT Response Address Byte A0 From TMP106 Frame 2 Slave Address Byte Figure 7.
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PACKAGE OPTION ADDENDUM www.ti.
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