Datasheet
TMP105
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SLLS648D –FEBRUARY 2005– REVISED SEPTEMBER 2011
SMBus ALERT FUNCTION
The TMP105 supports the SMBus Alert function. When the TMP105 is operating in Interrupt Mode (TM = 1), the
ALERT pin of the TMP105 may be connected as an SMBus Alert signal. When a master senses that an ALERT
condition is present on the ALERT line, the master sends an SMBus Alert command (00011001) on the bus. If
the ALERT pin of the TMP105 is active, the devices will acknowledge the SMBus Alert command and respond by
returning its slave address on the SDA line. The eighth bit (LSB) of the slave address byte will indicate if the
temperature exceeding T
HIGH
or falling below T
LOW
caused the ALERT condition. This bit will be HIGH if the
temperature is greater than or equal to T
HIGH
. This bit will be LOW if the temperature is less than T
LOW
. Refer to
Figure 7 for details of this sequence.
If multiple devices on the bus respond to the SMBus Alert command, arbitration during the slave address portion
of the SMBus Alert command will determine which device will clear its ALERT status. If the TMP105 wins the
arbitration, its ALERT pin will become inactive at the completion of the SMBus Alert command. If the TMP105
loses the arbitration, its ALERT pin will remain active.
GENERAL CALL
The TMP105 responds to a Two-Wire General Call address (0000000) if the eighth bit is 0. The device will
acknowledge the General Call address and respond to commands in the second byte. If the second byte is
00000100, the TMP105 will latch the status of the address pin, but will not reset. If the second byte is 00000110,
the TMP105 will latch the status of the address pin and reset the internal registers to their power-up values.
TIMEOUT FUNCTION
The TMP105 will reset the serial interface if either SCL or SDA are held LOW for 54ms (typ) between a START
and STOP condition. The TMP105 will release the bus if it is pulled LOW and will wait for a START condition. To
avoid activating the timeout function, it is necessary to maintain a communication speed of at least 1kHz for SCL
operating frequency.
TIMING DIAGRAMS
The TMP105 is Two-Wire and SMBus-compatible. Figure 4 to Figure 7 describe the various operations on the
TMP105. Bus definitions are given below. Parameters for Figure 4 are defined in Table 12.
Bus Idle:
Both SDA and SCL lines remain HIGH.
Start Data Transfer:
A change in the state of the SDA line, from HIGH to LOW, while the SCL line is HIGH, defines a START
condition. Each data transfer is initiated with a START condition.
Stop Data Transfer:
A change in the state of the SDA line from LOW to HIGH while the SCL line is HIGH defines a STOP condition.
Each data transfer is terminated with a repeated START or STOP condition.
Data Transfer:
The number of data bytes transferred between a START and a STOP condition is not limited and is determined
by the master device. The receiver acknowledges the transfer of data.
Acknowledge:
Each receiving device, when addressed, is obliged to generate an Acknowledge bit. A device that acknowledges
must pull down the SDA line during the Acknowledge clock pulse in such a way that the SDA line is stable LOW
during the HIGH period of the Acknowledge clock pulse. Setup and hold times must be taken into account. On a
master receive, the termination of the data transfer can be signaled by the master generating a Not-Acknowledge
on the last byte that has been transmitted by the slave.
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