Datasheet

TMP105

SLLS648D –FEBRUARY 2005– REVISED SEPTEMBER 2011

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BUS OVERVIEW

The device that initiates the transfer is called a master, and the devices controlled by the master are slaves. The

bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and

generates the START and STOP conditions.

To address a specific device, a START condition is initiated, indicated by pulling the data-line (SDA) from a

HIGH to LOW logic level while SCL is HIGH. All slaves on the bus shift in the slave address byte, with the last bit

indicating whether a read or write operation is intended. During the ninth clock pulse, the slave being addressed

responds to the master by generating an Acknowledge and pulling SDA LOW.

Data transfer is then initiated and sent over eight clock pulses followed by an Acknowledge Bit. During data

transfer SDA must remain stable while SCL is HIGH, as any change in SDA while SCL is HIGH will be

interpreted as a control signal.

Once all data has been transferred, the master generates a STOP condition, indicated by pulling SDA from LOW

to HIGH while SCL is HIGH.

WRITING/READING TO THE TMP105

Accessing a particular register on the TMP105 is accomplished by writing the appropriate value to the Pointer

bit LOW. Every write operation to the TMP105 requires a value for the Pointer Register. (Refer to Figure 5.)

When reading from the TMP105, the last value stored in the Pointer Register by a write operation is used to

determine which register is read by a read operation. To change the register pointer for a read operation, a new

value must be written to the Pointer Register. This is accomplished by issuing a slave address byte with the R/W

bit LOW, followed by the Pointer Register byte. No additional data are required. The master can then generate a

START condition and send the slave address byte with the R/W bit HIGH to initiate the read command. See

Figure 6 for details of this sequence. If repeated reads from the same register are desired, it is not necessary to

continually send the Pointer Register byte, as the TMP105 remembers the Pointer Register value until it is

changed by the next write operation.

Note that register bytes are sent most significant byte first, followed by the least significant byte.

SLAVE MODE OPERATIONS

The TMP105 can operate as a slave receiver or slave transmitter.

Slave Receiver Mode:

The first byte transmitted by the master is the slave address, with the R/W bit LOW. The TMP105 then

acknowledges reception of a valid address. The next byte transmitted by the master is the Pointer Register. The

TMP105 then acknowledges reception of the Pointer Register byte. The next byte or bytes are written to the

may terminate data transfer by generating a START or STOP condition.

Slave Transmitter Mode:

The first byte is transmitted by the master and is the slave address, with the R/W bit HIGH. The slave

acknowledges reception of a valid slave address. The next byte is transmitted by the slave and is the most

significant byte of the register indicated by the Pointer Register. The master acknowledges reception of the data

byte. The next byte transmitted by the slave is the least significant byte. The master acknowledges reception of

the data byte. The master may terminate data transfer by generating a Not-Acknowledge on reception of any

data byte, or generating a START or STOP condition.

Product Folder Link(s): TMP105