Datasheet

TMP102
www.ti.com SBOS397C –AUGUST 2007–REVISED OCTOBER 2012
CONVERTER RESOLUTION (R1/R0) Both operational modes are represented in Figure 10.
Table 10 and Table 11 describe the format for the
R1/R0 are read-only bits. The TMP102 converter
T
HIGH
and T
LOW
registers. Note that the most
resolution is set on start up to '11'. This sets the
significant byte is sent first, followed by the least
temperature register to a 12 bit-resolution.
significant byte. Power-up reset values for T
HIGH
and
T
LOW
are: T
HIGH
= +80°C and T
LOW
= +75°C. The
ONE-SHOT/CONVERSION READY (OS)
format of the data for T
HIGH
and T
LOW
is the same as
for the Temperature Register.
The TMP102 features a One-Shot Temperature
Measurement mode. When the device is in Shutdown
Table 10. Bytes 1 and 2 of T
HIGH
Register
(1)
mode, writing a ‘1’ to the OS bit starts a single
temperature conversion. During the conversion, the
BYTE D7 D6 D5 D4 D3 D2 D1 D0
OS bit reads '0'. The device returns to the shutdown
H11 H10 H9 H8 H7 H6 H5 H4
1
state at the completion of the single conversion. After
(H12) (H11) (H10) (H9) (H8) (H7) (H6) (H5)
the conversion, the OS bit reads '1'. This feature is
BYTE D7 D6 D5 D4 D3 D2 D1 D0
useful for reducing power consumption in the
TMP102 when continuous temperature monitoring is
H3 H2 H1 H0 0 0 0 0
2
not required.
(H4) (H3) (H2) (H1) (H0) (0) (0) (0)
As a result of the short conversion time, the TMP102
(1) Extended mode 13-bit configuration shown in parenthesis.
can achieve a higher conversion rate. A single
conversion typically takes 26ms and a read can take
Table 11. Bytes 1 and 2 of T
LOW
Register
(1)
place in less than 20μs. When using One-Shot mode,
BYTE D7 D6 D5 D4 D3 D2 D1 D0
30 or more conversions per second are possible.
L11 L10 L9 L8 L7 L6 L5 L4
1
(L12) (L11) (L10) (L9) (L8) (L7) (L6) (L5)
HIGH- AND LOW-LIMIT REGISTERS
BYTE D7 D6 D5 D4 D3 D2 D1 D0
In Comparator mode (TM = 0), the ALERT pin
L3 L2 L1 L0 0 0 0 0
becomes active when the temperature equals or
2
(L4) (L3) (L2) (L1) (L0) (0) (0) (0)
exceeds the value in T
HIGH
and generates a
consecutive number of faults according to fault bits
(1) Extended mode 13-bit configuration shown in parenthesis.
F1 and F0. The ALERT pin remains active until the
temperature falls below the indicated T
LOW
value for
BUS OVERVIEW
the same number of faults.
The device that initiates the transfer is called a
In Interrupt mode (TM = 1), the ALERT pin becomes
master, and the devices controlled by the master are
active when the temperature equals or exceeds the
slaves. The bus must be controlled by a master
value in T
HIGH
for a consecutive number of fault
device that generates the serial clock (SCL), controls
conditions (as shown in Table 9). The ALERT pin
the bus access, and generates the START and STOP
remains active until a read operation of any register
conditions.
occurs, or the device successfully responds to the
To address a specific device, a START condition is
SMBus Alert Response address. The ALERT pin will
initiated, indicated by pulling the data-line (SDA) from
also be cleared if the device is placed in Shutdown
a high to low logic level while SCL is high. All slaves
mode. Once the ALERT pin is cleared, it becomes
on the bus shift in the slave address byte on the
active again only when temperature falls below T
LOW
,
rising edge of the clock, with the last bit indicating
and remains active until cleared by a read operation
whether a read or write operation is intended. During
of any register or a successful response to the
the ninth clock pulse, the slave being addressed
SMBus Alert Response address. Once the ALERT
responds to the master by generating an
pin is cleared, the above cycle repeats, with the
Acknowledge and pulling SDA low.
ALERT pin becoming active when the temperature
equals or exceeds T
HIGH
. The ALERT pin can also be
Data transfer is then initiated and sent over eight
cleared by resetting the device with the General Call
clock pulses followed by an Acknowledge Bit. During
Reset command. This action also clears the state of
data transfer SDA must remain stable while SCL is
the internal registers in the device, returning the
high, because any change in SDA while SCL is high
device to Comparator mode (TM = 0).
will be interpreted as a START or STOP signal.
Once all data have been transferred, the master
generates a STOP condition indicated by pulling SDA
from low to high, while SCL is high.
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