Datasheet

NOTE:(1)ThevalueofA0andA1aredeterminedbytheADD0pin.
Frame1SMBusALERTResponseAddressByte Frame2SlaveAddressFrom Device
StartBy
Master
ACKBy
Device
From
Device
NACKBy
Master
StopBy
Master
1 9 1
9
SDA
SCL
ALERT
0 0 0 1 1 0 0 R/W
1 0 0 1 A1 A0 Status
Frame1Two-WireSlaveAddressByte Frame2PointerRegisterByte
1
StartBy
Master
ACKBy
Device
ACKBy
Device
Frame3Two-WireSlaveAddressByte Frame4DataByte1ReadRegister
StartBy
Master
ACKBy
Device
ACKBy
Master
(2)
From
Device
1 9 1
9
1 9 1
9
SDA
SCL
0 0 1 R/W
0 0 0 0 0 0 P1 P0
¼
¼
¼
SDA
(Continued)
SCL
(Continued)
SDA
(Continued)
SCL
(Continued)
1 0 0 1
0 A1
(1)
A0
(1)
0
A1
(1)
A0
(1)
R/W
D7 D6 D5 D4 D3 D2 D1 D0
Frame5DataByte2ReadRegister
StopBy
Master
ACKBy
Master
(3)
From
Device
1
9
D7 D6 D5 D4 D3 D2 D1 D0
StopBy
Master
NOTE: (1)ThevalueofA0andA1aredeterminedbytheADD0pin.
(2)MastershouldleaveSDAhightoterminateasingle-bytereadoperation.
(3)MastershouldleaveSDAhightoterminateatwo-bytereadoperation.
TMP102
SBOS397C –AUGUST 2007–REVISED OCTOBER 2012 www.ti.com
Figure 14. Two-Wire Timing Diagram for Read Word Format
Figure 15. Timing Diagram for SMBus ALERT
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