Datasheet

Frame1Two-WireSlaveAddressByte
Frame2PointerRegisterByte
Frame4DataByte2
1
StartBy
Master
ACKBy
Device
ACKBy
Device
ACKBy
Device
StopBy
Master
1 9 1
1
D7 D6 D5 D4 D3 D2 D1 D0
9
Frame3DataByte1
ACKBy
Device
1
D7
SDA
(Continued)
SCL
(Continued)
D6 D5 D4 D3 D2 D1 D0
9
9
SDA
SCL
0 0 1 0
A1
(1)
A0
(1)
R/W
0 0 0 0 0 0 P1 P0 ¼
¼
NOTE:(1)ThevalueofA0andA1aredeterminedbytheADD0pin.
SCL
SDA
t
(LOW)
t
R
t
F
t
(HDSTA)
t
(HDSTA)
t
(HDDAT)
t
(BUF)
t
(SUDAT)
t
(HIGH)
t
(SUSTA)
t
(SUSTO)
P S S P
TMP102
www.ti.com SBOS397C –AUGUST 2007–REVISED OCTOBER 2012
TWO-WIRE TIMING DIAGRAMS
Figure 12. Two-Wire Timing Diagram
Figure 13. Two-Wire Timing Diagram for Write Word Format
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