Datasheet

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SBOS231G − JANUARY 2002 − REVISED NOVEMBER 2007
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7
Table 7. Fault Settings of the TMP100 and
TMP101
F1 F0 CONSECUTIVE FAULTS
0 0 1
0 1 2
1 0 4
1 1 6
CONVERTER RESOLUTION (R1/R0)
The Converter Resolution Bits control the resolution of the
internal Analog-to-Digital (A/D) converter. This allows the
user to maximize efficiency by programming for higher
resolution or faster conversion time. Table 8 identifies the
Resolution Bits and relationship between resolution and
conversion time.
Table 8. Resolution of the TMP100 and TMP101
R1 R0 RESOLUTION
CONVERSION TIME
(typical)
0 0 9 Bits (0.5°C) 40ms
0 1 10 Bits (0.25°C) 80ms
1 0 11 Bits (0.125°C) 160ms
1 1 12 Bits (0.0625°C) 320ms
OS/ALERT (OS)
The TMP100 and TMP101 feature a One-Shot
Temperature Measurement Mode. When the device is in
Shutdown Mode, writing a 1 to the OS/ALERT bit will start
a single temperature conversion. The device will return to
the shutdown state at the completion of the single
conversion. This is useful to reduce power consumption in
the TMP100 and TMP101 when continuous monitoring of
temperature is not required.
Reading the OS/ALERT bit will provide information about
the Comparator Mode status. The state of the POL bit will
invert the polarity of data returned from the OS/ALERT bit.
For POL = 0, the OS/ALERT will read as 1 until the
temperature equals or exceeds T
HIGH
for the programmed
number of consecutive faults, causing the OS/ALERT bit
to read as 0. The OS/ALERT bit will continue to read as 0
until the temperature falls below T
LOW
for the programmed
number of consecutive faults when it will again read as 1.
The status of the TM bit does not affect the status of the
OS/ALERT bit.
HIGH AND LOW LIMIT REGISTERS
In Comparator Mode (TM = 0), the ALERT pin of the
TMP101 becomes active when the temperature equals or
exceeds the value in T
HIGH
and generates a consecutive
number of faults according to fault bits F1 and F0. The
ALERT pin will remain active until the temperature falls
below the indicated T
LOW
value for the same number of
faults.
In Interrupt Mode (TM = 1) the ALERT Pin becomes active
when the temperature equals or exceeds T
HIGH
for a
consecutive number of fault conditions. The ALERT pin
remains active until a read operation of any register occurs
or the device successfully responds to the SMBus Alert
Response Address. The ALERT pin will also be cleared if
the device is placed in Shutdown Mode. Once the ALERT
pin is cleared, it will only become active again by the
temperature falling below T
LOW
. When the temperature
falls below T
LOW
, the ALERT pin will become active and
remain active until cleared by a read operation of any
register or a successful response to the SMBus Alert
Response Address. Once the ALERT pin is cleared, the
above cycle will repeat with the ALERT pin becoming
active when the temperature equals or exceeds T
HIGH
.
The ALERT pin can also be cleared by resetting the device
with the General Call Reset command. This will also clear
the state of the internal registers in the device returning the
device to Comparator Mode (TM = 0).
Both operational modes are represented in Figure 4.
Table 9 and Table 10 describe the format for the T
HIGH
and
T
LOW
registers. Power-up Reset values for T
HIGH
and
T
LOW
are: T
HIGH
= 80°C and T
LOW
= 75°C. The format of
the data for T
HIGH
and T
LOW
is the same as for the
Temperature Register.
Table 9. Bytes 1 and 2 of T
HIGH
Register
BYTE D7 D6 D5 D4 D3 D2 D1 D0
1 H11 H10 H9 H8 H7 H6 H5 H4
BYTE D7 D6 D5 D4 D3 D2 D1 D0
2 H3 H2 H1 H0 0 0 0 0
Table 10. Bytes 1 and 2 of T
LOW
Register
BYTE D7 D6 D5 D4 D3 D2 D1 D0
1 L11 L10 L9 L8 L7 L6 L5 L4
BYTE D7 D6 D5 D4 D3 D2 D1 D0
2 L3 L2 L1 L0 0 0 0 0
All 12 bits for the Temperature, T
HIGH
, and T
LOW
registers
are used in the comparisons for the ALERT function for all
converter resolutions. The three LSBs in T
HIGH
and T
LOW
can affect the ALERT output even if the converter is
configured for 9-bit resolution.
SERIAL INTERFACE
The TMP100 and TMP101 operate only as slave devices
on the I
2
C bus and SMBus. Connections to the bus are
made via the open-drain I/O lines SDA and SCL. The
TMP100 and TMP101 support the transmission protocol
for fast (up to 400kHz) and high-speed (up to 3.4MHz)
modes. All data bytes are transmitted most significant bit
first.