Datasheet

TMP100−EP
DIGITAL TEMPERATURE SENSOR
WITH I
2
C INTERFACE
SGLS254B − JULY 2005 − REVISED OCTOBER 2013
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge bit. A device
that acknowledges must pull down the SDA line during the Acknowledge clock pulse in such a way that the SDA
line is stable low during the high period of the acknowledge clock pulse. Setup and hold times must be taken
into account. On a master receive, the termination of the data transfer can be signaled by the master generating
a not-acknowledge on the last byte that has been transmitted by the slave.
PARAMETER
FAST MODE HIGH-SPEED MODE
UNIT
PARAMETER
MIN MAX MIN MAX
UNIT
f
(SCLK)
SLCK operating frequency 0.4 3.4 MHz
t
(BUF)
Bus free time between STOP and START condition 600 160 ns
t
h(STA)
Hold time after repeated START condition. After this period, the
first clock is generated.
600 160 ns
t
su(STA)
Repeated START condition setup time 600 160 ns
t
su(STO)
STOP condition setup time 600 160 ns
t
h(DAT)
Data hold time 0 0 ns
t
su(DAT)
Data setup time 100 10 ns
t
(LOW)
SCLK clock low period 1300 160 ns
t
(HIGH)
SCLK clock high period 600 60 ns
t
f
Clock/data fall time 300 160 ns
t
r
Clock/data rise time 300 160 ns
Table 12. Timing Diagram Definitions
P S S P
SCL
SDA
t
(BUF)
t
h(STA)
t
r
t
(LOW)
t
h(DAT)
t
f
t
(HIGH)
t
su(DAT)
t
su(STA)
t
h(STA)
t
su(STO)
Figure 4. I
2
C Timing Diagram