Datasheet

TMP100−EP
DIGITAL TEMPERATURE SENSOR
WITH I
2
C INTERFACE
SGLS254B − JULY 2005 − REVISED OCTOBER 2013
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
SMBus alert function
The TMP101 supports the SMBus Alert function. When the TMP101 is operating in Interrupt Mode (TM = 1),
the ALERT pin of the TMP101 may be connected as an SMBus Alert signal. When a master senses that an
ALERT condition is present on the ALERT line, the master sends an SMBus Alert command (00011001) on the
bus. If the ALERT pin of the TMP101 is active, the TMP101 acknowledges the SMBus Alert command and
responds by returning its slave address on the SDA line. The eighth bit (LSB) of the slave address byte indicates
if the temperature exceeding T
HIGH
or falling below T
LOW
caused the ALERT condition. For POL = 0, this bit
will be LOW if the temperature is greater than or equal to T
HIGH
. This bit will be HIGH if the temperature is less
than T
LOW
. The polarity of this bit will be inverted if POL = 1. See Figure 7 for details of this sequence.
If multiple devices on the bus respond to the SMBus Alert command, arbitration during the slave address portion
of the SMBus alert command determines which device clears its ALERT status. If the TMP101 wins the
arbitration, its ALERT pin becomes inactive at the completion of the SMBus Alert command. If the TMP101 loses
the arbitration, its ALERT pin remains active.
The TMP100 also responds to the SMBus ALERT command if its TM bit is set to 1. Since it does not have an
ALERT pin, the master needs to periodically poll the device by issuing an SMBus Alert command. If the TMP100
has generated an ALERT, it acknowledges the SMBus Alert command and returns its slave address in the next
byte.
general call
The TMP100 and TMP101 respond to the I
2
C General Call address (0000000) if the eighth bit is 0. The device
acknowledges the general call address and responds to commands in the second byte. If the second byte is
00000100, the TMP100 and TMP101 latch the status of their address pins, but will not reset. If the second byte
is 00000110, the TMP100 and TMP101 latch the status of their address pins and reset their internal registers.
high-speed mode
In order for the I
2
C bus to operate at frequencies above 400 kHz, the master device must issue an Hs-mode
master code (00001XXX) as the first byte after a START condition to switch the bus to high-speed operation.
The TMP100 and TMP101 will not acknowledge this byte as required by the I
2
C specification, but switch their
input filters on SDA and SCL and their output filters on SDA to operate in Hs-mode, allowing transfers at up to
3.4 MHz. After the Hs-mode master code has been issued, the master transmits an I
2
C slave address to initiate
a data transfer operation. The bus continues to operate in Hs-mode until a STOP condition occurs on the bus.
Upon receiving the STOP condition, the TMP100 and TMP101 switch their input and output filters back to
fast-mode operation.
timing diagrams
The TMP100 and TMP101 are I
2
C and SMBus compatible. Figure 4 through Figure 7 describe the various
operations on the TMP100 and TMP101. Bus definitions are given below. Parameters for Figure 4 are defined
in Table 12.
Bus Idle: Both SDA and SCL lines remain high.
Start Data Transfer: A change in the state of the SDA line, from high-to-low, while the SCL line is high, defines
a START condition. Each data transfer is initiated with a START condition.
Stop Data Transfer: A change in the state of the SDA line from low-to-high while the SCL line is high defines
a STOP condition. Each data transfer is terminated with a repeated START or STOP condition.
Data Transfer: The number of data bytes transferred between a START and a STOP condition is not limited
and is determined by the master device. The receiver acknowledges the transfer of data.