Datasheet

TMP100−EP
DIGITAL TEMPERATURE SENSOR
WITH I
2
C INTERFACE
SGLS254B − JULY 2005 − REVISED OCTOBER 2013
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
bus overview
The device that initiates the transfer is called a master and the devices controlled by the master are slaves. The
bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and
generates the START and STOP conditions.
To address a specific device, a START condition is initiated, indicated by pulling the data-line (SDA) from a
high-to-low logic level while SCL is high. All slaves on the bus shift in the slave address byte, with the last bit
indicating whether a read or write operation is intended. During the ninth clock pulse, the slave being addressed
responds to the master by generating an acknowledge and pulling SDA low.
Data transfer is then initiated and sent over eight clock pulses followed by an acknowledge bit. During data
transfer, SDA must remain stable while SCL is high, as any change in SDA while SCL is high will be interpreted
as a control signal. Once all data has been transferred, the master generates a STOP condition indicated by
pulling SDA from low-to-high, while SCL is high.
writing/reading to the TMP100 and TMP101
Accessing a particular register on the TMP100 and TMP101 is accomplished by writing the appropriate value
to the pointer register. The value for the pointer register is the first byte transferred after the I
2
C slave address
byte with the R/W bit low. Every write operation to the TMP100 and TMP101 requires a value for the pointer
register. (See Figure 5.)
When reading from the TMP100 and TMP101, the last value stored in the pointer register by a write operation
is used to determine which register is read by a read operation. To change the register pointer for a read
operation, a new value must be written to the pointer register. This is accomplished by issuing an I
2
C slave
address byte with the R/W bit low, followed by the pointer register byte. No additional data is required. The
master can then generate a START condition and send the I
2
C slave address byte with the R/W bit high to initiate
the read command. See Figure 6 for details of this sequence. If repeated reads from the same register are
desired, it is not necessary to continually send the pointer register bytes as the TMP100 and TMP101
remembers the pointer register value until it is changed by the next write operation.
slave mode operations
The TMP100 and TMP101 can operate as slave receivers or slave transmitters.
slave receiver mode
The first byte transmitted by the master is the slave address, with the R/W bit low. The TMP100 or TMP101 then
acknowledges reception of a valid address. The next byte transmitted by the master is the pointer register. The
TMP100 or TMP101 then acknowledges reception of the pointer register byte. The next byte or bytes are written
to the register addressed by the pointer register. The TMP100 and TMP101 acknowledge reception of each data
byte. The master may terminate data transfer by generating a START or STOP condition.
slave transmitter mode
The first byte is transmitted by the master and is the slave address, with the R/W bit high. The slave
acknowledges reception of a valid slave address. The next byte is transmitted by the slave and is the most
significant byte of the register indicated by the pointer register. The master acknowledges reception of the data
byte. The next byte transmitted by the slave is the least significant byte. The master acknowledges reception
of the data byte. The master may terminate data transfer by generating a not-acknowledge on reception of any
data byte, or generating a START or STOP condition.