Datasheet

EMIF_CLK
EMIF_BA[1:0]
EMIF_ADDR[21:0]
EMIF_DATA[15:0]
1
2 2
4
6
8
8
12
10
16
3
5
7
7
11
13
15
9
BASIC SDRAM
WRITE OPERATION
EMIF_CS[0]
EMIF_DQM[1:0]
EMIF_nRAS
EMIF_nCAS
EMIF_nWE
RM46L450
RM46L850
www.ti.com SPNS184A –SEPTEMBER 2012–REVISED SEPTEMBER 2013
Figure 4-17. Basic SDRAM Write Operation
Table 4-30. EMIF Synchronous Memory Timing Requirements
NO. Parameter MIN MAX Unit
19 t
su(EMIFDV-EM_CLKH)
Input setup time, read data valid on 2 ns
EMIFDATA[15:0] before EMIF_CLK
rising
20 t
h(CLKH-DIV)
Input hold time, read data valid on 2 ns
EMIFDATA[15:0] after EMIF_CLK
rising
Table 4-31. EMIF Synchronous Memory Switching Characteristics
NO. Parameter MIN MAX Unit
1 t
c(CLK)
Cycle time, EMIF clock EMIF_CLK 20 ns
2 t
w(CLK)
Pulse width, EMIF clock EMIF_CLK 5 ns
high or low
3 t
d(CLKH-CSV)
Delay time, EMIF_CLK rising to 13 ns
EMIFnCS[0] valid
4 t
oh(CLKH-CSIV)
Output hold time, EMIF_CLK rising to 1 ns
EMIFnCS[0] invalid
5 t
d(CLKH-DQMV)
Delay time, EMIF_CLK rising to 13 ns
EMIFnDQM[1:0] valid
6 t
oh(CLKH-DQMIV)
Output hold time, EMIF_CLK rising to 1 ns
EMIFnDQM[1:0] invalid
7 t
d(CLKH-AV)
Delay time, EMIF_CLK rising to 13 ns
EMIFADDR[21:0] and EMIFBA[1:0]
valid
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