Datasheet

EMIF_CLK
EMIF_BA[1:0]
EMIF_ADDR[21:0]
EMIF_DATA[15:0]
1
2 2
4
6
8
8
12
14
19
20
3
5
7
7
11
13
17
18
2 EM_CLK Delay
BASIC SDRAM
READ OPERATION
EMIF_nCS[0]
EMIF_nDQM[1:0]
EMIF_nRAS
EMIF_nCAS
EMIF_nWE
RM46L450
RM46L850
SPNS184A –SEPTEMBER 2012–REVISED SEPTEMBER 2013 www.ti.com
4.14.2.2 Synchronous Timing
Figure 4-16. Basic SDRAM Read Operation
96 System Information and Electrical Specifications Copyright © 2012–2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: RM46L450 RM46L850