Datasheet

RM46L450
RM46L850
www.ti.com SPNS184A –SEPTEMBER 2012–REVISED SEPTEMBER 2013
1 RM46Lx50 16- and 32-Bit RISC Flash 4.10 Flash Memory ...................................... 84
Microcontroller .......................................... 1
4.11 Tightly-Coupled RAM Interface Module ............ 87
1.1 Features ............................................. 1
4.12 Parity Protection for Accesses to peripheral RAMs 87
1.2 Applications .......................................... 2
4.13 On-Chip SRAM Initialization and Testing ........... 89
1.3 Description ........................................... 3
4.14 External Memory Interface (EMIF) ................. 91
1.4 Functional Block Diagram ........................... 5
4.15 Vectored Interrupt Manager ........................ 99
Revision History .............................................. 8
4.16 DMA Controller .................................... 103
2 Device Package and Terminal Functions .......... 9
4.17 Real Time Interrupt Module ....................... 106
2.1 PGE QFP Package Pinout (144-Pin) ................ 9
4.18 Error Signaling Module ............................ 108
2.2 ZWT BGA Package Ball-Map (337 Ball Grid Array) 10
4.19 Reset / Abort / Error Sources ..................... 112
2.3 Terminal Functions ................................. 11
4.20 Digital Windowed Watchdog ...................... 115
3 Device Operating Conditions ....................... 49
4.21 Debug Subsystem ................................. 116
3.1 Absolute Maximum Ratings Over Operating Free-
5 Peripheral Information and Electrical
Air Temperature Range, ............................ 49
Specifications ......................................... 121
3.2 Device Recommended Operating Conditions ...... 49
5.1 Enhanced Translator PWM Modules (ePWM) .... 121
3.3 Switching Characteristics over Recommended
5.2 Enhanced Capture Modules (eCAP) .............. 126
Operating Conditions for Clock Domains .......... 50
5.3 Enhanced Quadrature Encoder (eQEP) .......... 128
3.4 Wait States Required ............................... 50
5.4 Multi-Buffered 12bit Analog-to-Digital Converter .. 130
3.5 Power Consumption Over Recommended
5.5 General-Purpose Input/Output .................... 141
Operating Conditions ............................... 51
5.6 Enhanced High-End Timer (N2HET) .............. 142
3.6 Input/Output Electrical Characteristics Over
Recommended Operating Conditions .............. 52
5.7 Controller Area Network (DCAN) .................. 146
3.7 Output Buffer Drive Strengths ...................... 53
5.8 Local Interconnect Network Interface (LIN) ....... 147
3.8 Input Timings ....................................... 54
5.9 Serial Communication Interface (SCI) ............ 148
3.9 Output Timings ..................................... 54
5.10 Inter-Integrated Circuit (I2C) ...................... 149
3.10 Low-EMI Output Buffers ............................ 56
5.11 Multi-Buffered / Standard Serial Peripheral Interface
..................................................... 152
4 System Information and Electrical Specifications
............................................................. 57
5.12 Ethernet Media Access Controller ................ 164
4.1 Device Power Domains ............................ 57
5.13 Universal Serial Bus Controller ................... 168
4.2 Voltage Monitor Characteristics .................... 57
6 Device and Documentation Support ............. 170
6.1 Device and Development-Support Tool
4.3 Power Sequencing and Power On Reset .......... 59
Nomenclature ..................................... 170
4.4 Warm Reset (nRST) ................................ 61
6.2 Community Resources ............................ 170
4.5 ARM
©
Cortex-R4F™ CPU Information ............. 62
6.3 Device Identification ............................... 171
4.6 Clocks .............................................. 65
6.4 Module Certifications .............................. 173
4.7 Clock Monitoring .................................... 74
7 Mechanical Data ...................................... 178
4.8 Glitch Filters ........................................ 76
7.1 Thermal Data ...................................... 178
4.9 Device Memory Map ................................ 77
7.2 Packaging Information ............................ 178
Copyright © 2012–2013, Texas Instruments Incorporated Contents 7
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