Datasheet

Address Waitstates
Data Waitstates
RAM
Address Waitstates
Data Waitstates
Flash (main memory)
0MHz
0MHz
0MHz
0MHz
50MHz
0 1 3
0
0
0
150MHz
2
150MHz
1
f
HCLK(max)
f
HCLK(max)
f
HCLK(max)
f
HCLK(max)
Data Waitstates
0MHz
0 1 3
150MHz
2
f
HCLK(max)
Flash (data memory)
100MHz
50MHz 100MHz
RM46L450
RM46L850
SPNS184A –SEPTEMBER 2012–REVISED SEPTEMBER 2013 www.ti.com
3.3 Switching Characteristics over Recommended Operating Conditions for Clock Domains
Table 3-1. Clock Domain Timing Specifications
Parameter Description Conditions Max Unit
f
HCLK
HCLK - System clock frequency Pipeline mode 200 MHz
enabled
Pipeline mode 50 MHz
disabled
f
GCLK
GCLK - CPU clock frequency f
HCLK
MHz
f
VCLK
VCLK - Primary peripheral clock frequency 100 MHz
f
VCLK2
VCLK2 - Secondary peripheral clock 100 MHz
frequency
f
VCLK3
VCLK3 - Secondary peripheral clock 100 MHz
frequency
f
VCLKA1
VCLKA1 - Primary asynchronous 100 MHz
peripheral clock frequency
f
VCLKA2
VCLKA2 - Secondary asynchronous 100 MHz
peripheral clock frequency
f
VCLKA3
VCLKA3 - Primary asynchronous 100 MHz
peripheral clock frequency
f
VCLKA4
VCLKA4 - Secondary asynchronous 100 MHz
peripheral clock frequency
f
RTICLK
RTICLK - clock frequency f
VCLK
MHz
3.4 Wait States Required
Figure 3-1. Wait States Scheme
As shown in the figure above, the TCM RAM can support program and data fetches at full CPU speed without
any address or data wait states required.
The TCM flash can support zero address and data wait states up to a CPU speed of 50MHz in non-pipelined
mode. The flash supports a maximum CPU clock speed of 200MHz in pipelined mode with one address wait
state and three data wait states.
The flash wrapper defaults to non-pipelined mode with zero address wait state and one random-read data wait
state.
50 Device Operating Conditions Copyright © 2012–2013, Texas Instruments Incorporated
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