Datasheet
RM46L450
RM46L850
SPNS184A –SEPTEMBER 2012–REVISED SEPTEMBER 2013
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2.3.2.12 Multi-Buffered Serial Peripheral Interface Modules (MibSPI)
Table 2-36. ZWT Multi-Buffered Serial Peripheral Interface Modules (MibSPI)
Terminal Signal Default Pull Type Description
Type Pull State
Signal Name 337
ZWT
MIBSPI1CLK F18 I/O Pull Up Programmable, MibSPI1 clock, or GPIO
20 µA
MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2]/ R2 MibSPI1 chip select, or
USB1.RCV GPIO
MIBSPI1NCS[1]/N2HET1[17]/MII_COL/ F3
USB1.SUSPEND /EQEP1S
MIBSPI1NCS[2]/N2HET1[19]/MDIO G3
MIBSPI1NCS[3]/N2HET1[21] J3
N2HET1[15]/MIBSPI1NCS[4] N1 Pull Down Programmable, MibSPI1 chip select, or
20 µA GPIO
N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0]/RMII_RXD[0] P1
MIBSPI1NENA/N2HET1[23]/MII_RXD[2]/ G19 Pull Up Programmable, MibSPI1 enable, or GPIO
USB1.VP/ECAP4 20 µA
MIBSPI1SIMO[0] F19 MibSPI1 slave-in master-
out, or GPIO
N2HET1[08]/MIBSPI1SIMO[1]/MII_TXD[3]/USB1.OverCurrent E18 Pull Down Programmable, MibSPI1 slave-in master-
20 µA out, or GPIO
MIBSPI1SOMI[0] G18 Pull Up Programmable, MibSPI1 slave-out master-
20 µA in, or GPIO
MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2]/ECAP6/ R2
USB1.RCV
MIBSPI3CLK/AWM1_EXT_SEL[1]/EQEP1A V9 I/O Pull Up Programmable, MibSPI3 clock, or GPIO
20 µA
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/EQEP1I/N2HET2_PIN_nD V10 MibSPI3 chip select, or
IS GPIO
MIBSPI3NCS[1]/N2HET1[25]/MDCLK V5
MIBSPI3NCS[2]/I2C_SDA/N2HET1[27]/nTZ2 B2
MIBSPI3NCS[3]/I2C_SCL/N2HET1[29]/nTZ1 C3
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/ E3 Pull Down Programmable, MibSPI3 chip select, or
USB2.OverCurrent/USB_FUNC.VBUSI/EPWM1SYNCO 20 µA GPIO
MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]/EQEP1B W9 Pull Up Programmable, MibSPI3 chip select, or
20 µA GPIO
MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]/EQEP1B W9 MibSPI3 enable, or GPIO
MIBSPI3SIMO[0]/AWM1_EXT_SEL[0]/ECAP3 W8 MibSPI3 slave-in master-
out, or GPIO
MIBSPI3SOMI[0]/AWM1_EXT_ENA/ECAP2 V8 MibSPI3 slave-out master-
in, or GPIO
34 Device Package and Terminal Functions Copyright © 2012–2013, Texas Instruments Incorporated
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