Datasheet

SPICLK
(clock polarity=0)
SPICSn
8
SPICLK
(clock polarity=1)
SPIENAn
9
SPISOMI
SPICLK
(clockpolarity=1)
SPICLK
(clockpolarity=0)
3
2
1
5
4
7
SPISIMOData
MustBeValid
SPISOMIDataIsValid
666
SPISIMO
RM46L450
RM46L850
www.ti.com SPNS184A –SEPTEMBER 2012–REVISED SEPTEMBER 2013
Figure 5-18. SPI Slave Mode External Timing (CLOCK PHASE = 0)
Figure 5-19. SPI Slave Mode Enable Timing (CLOCK PHASE = 0)
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