Datasheet

RM46L450
RM46L850
www.ti.com SPNS184A –SEPTEMBER 2012–REVISED SEPTEMBER 2013
Table 5-12. Device-Level Input Connection to eCAPx Modules
Input Signal Control for Double-Synchronized Connection to Control for Double-Synchronized and Filtered
eQEPx Connection to eQEPx
eQEP1A PINMMR44[16] = 1 PINMMR44[16] = 0 and PINMMR44[17] = 1
eQEP1B PINMMR44[24] = 1 PINMMR44[24] = 0 and PINMMR44[25] = 1
eQEP1I PINMMR45[0] = 1 PINMMR45[0] = 0 and PINMMR45[1] = 1
eQEP1S PINMMR45[8] = 1 PINMMR45[8] = 0 and PINMMR45[9] = 1
eQEP2A PINMMR45[16] = 1 PINMMR45[16] = 0 and PINMMR45[17] = 1
eQEP2B PINMMR45[24] = 1 PINMMR45[24] = 0 and PINMMR45[25] = 1
eQEP2I PINMMR46[0] = 1 PINMMR46[0] = 0 and PINMMR46[1] = 1
eQEP2S PINMMR46[8] = 1 PINMMR46[8] = 0 and PINMMR46[9] = 1
5.3.4 Enhanced Quadrature Encoder Pulse (eQEPx) Timing
Table 5-13. eQEPx Timing Requirements
PARAMETER TEST CONDITIONS MIN MAX UNIT
t
w(QEPP)
QEP input period Synchronous 2 t
c(VCLK4)
cycles
Synchronous, with input 2 t
c(VCLK4)
+ filter width cycles
filter
t
w(INDEXH)
QEP Index Input High Time Synchronous 2 t
c(VCLK4)
cycles
Synchronous, with input 2 t
c(VCLK4)
+ filter width cycles
filter
t
w(INDEXL)
QEP Index Input Low Time Synchronous 2 t
c(VCLK4)
cycles
Synchronous, with input 2 t
c(VCLK4)
+ filter width cycles
filter
t
w(STROBH)
QEP Strobe Input High Time Synchronous 2 t
c(VCLK4)
cycles
Synchronous, with input 2 t
c(VCLK4)
+ filter width cycles
filter
t
w(STROBL)
QEP Strobe Input Low Time Synchronous 2 t
c(VCLK4)
cycles
Synchronous, with input 2 t
c(VCLK4)
+ filter width cycles
filter
Table 5-14. eQEPx Switching Characteristics
PARAMETER MIN MAX UNIT
t
d(CNTR)xin
Delay time, external clock to counter increment 4 t
c(VCLK4)
cycles
t
d(PCS-OUT)QEP
Delay time, QEP input edge to position compare sync output 6 t
c(VCLK4)
cycles
Copyright © 2012–2013, Texas Instruments Incorporated Peripheral Information and Electrical Specifications 129
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