Datasheet

RM46L450
RM46L850
www.ti.com SPNS184A –SEPTEMBER 2012–REVISED SEPTEMBER 2013
2.3 Terminal Functions
Section 2.3.1 and Section 2.3.2 identify the external signal names, the associated pin/ball numbers along
with the mechanical package designator, the pin/ball type (Input, Output, IO, Power or Ground), whether
the pin/ball has any internal pullup/pulldown, whether the pin/ball can be configured as a GPIO, and a
functional pin/ball description. The first signal name listed is the primary function for that terminal. The
signal name in Bold is the function being described. Refer to the I/O Multiplexing Module (IOMM) chapter
of the Technical Reference Manual .
NOTE
All I/O signals except nRST are configured as inputs while nPORRST is low and immediately
after nPORRST goes High.
All output-only signals are tri-stated while nPORRST is low, and are configured as outputs
immediately after nPORRST goes High.
While nPORRST is low, the input buffers are disabled, and the output buffers are tri-stated.
In the Terminal Functions table below, the "Default Pull State" is the state of the pull applied
to the terminal while nPORRST is low and immediately after nPORRST goes High. The
default pull direction may change when software configures the pin for an alternate function.
The "Pull Type" is the type of pull asserted when the signal name in bold is enabled for the
given terminal by the IOMM control registers.
2.3.1 PGE Package
2.3.1.1 Multi-Buffered Analog-to-Digital Converters (MibADC)
Table 2-1. PGE Multi-Buffered Analog-to-Digital Converters (MibADC1, MibADC2)
Terminal Signal Default Pull Type Description
Type Pull State
Signal Name 144
PGE
ADREFHI
(1)
66 Power - None ADC high reference
supply
ADREFLO
(1)
67 Power ADC low reference supply
VCCAD
(1)
69 Power Operating supply for ADC
VSSAD
(1)
68 Ground
AD1EVT/MII_RX_ER/RMII_RX_ER 86 I/O Pull Down Programmable, ADC1 event trigger input,
20 µA or GPIO
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/ 55 I/O Pull Up Programmable, ADC2 event trigger input,
EQEP1I/N2HET2_PIN_nDIS 20 µA or GPIO
AD1IN[0] 60 Input - None ADC1 analog input
AD1IN[01] 71
AD1IN[02] 73
AD1IN[03] 74
AD1IN[04] 76
AD1IN[05] 78
AD1IN[06] 80
AD1IN[07] 61
(1) The ADREFHI, ADREFLO, VCCAD and VSSAD connections are common for both ADC cores.
Copyright © 2012–2013, Texas Instruments Incorporated Device Package and Terminal Functions 11
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