Datasheet

AM1808
SPRS653E FEBRUARY 2010REVISED MARCH 2014
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Table 3-26. Video Port Interface (VPIF) Terminal Functions (continued)
SIGNAL
POWER
TYPE
(1)
PULL
(2)
DESCRIPTION
GROUP
(3)
NAME NO.
VP_CLKIN3 / MMCSD1_DAT[1] / PRU1_R30[1] / GP6[2] / VPIF display channel 3
J3 I CP[30] C
PRU1_R31[2] input clock
VPIF display channel 3
VP_CLKOUT3 / PRU1_R30[0] / GP6[1] / PRU1_R31[1] K4 O CP[30] C
output clock
VP_DOUT[15] / LCD_D[15] / UPP_XD[7] / GP7[7] / BOOT[7] P4 O CP[29] C
VP_DOUT[14] / LCD_D[14] / UPP_XD[6]/ GP7[6] / BOOT[6] R3 O CP[29] C
VP_DOUT[13] / LCD_D[13] / UPP_XD[5] / GP7[5] / BOOT[5] R2 O CP[29] C
VP_DOUT[12] / LCD_D[12] / UPP_XD[4] / GP7[4] / BOOT[4] R1 O CP[29] C
VP_DOUT[11] / LCD_D[11] / UPP_XD[3] / GP7[3] / BOOT[3] T3 O CP[29] C
VP_DOUT[10] / LCD_D[10] / UPP_XD[2] / GP7[2] / BOOT[2] T2 O CP[29] C
VP_DOUT[9] / LCD_D[9] / UPP_XD[1] / GP7[1] / BOOT[1] T1 O CP[29] C
VP_DOUT[8] / LCD_D[8] / UPP_XD[1] / GP7[0] / BOOT[0] U3 O CP[29] C
VPIF display data bus
VP_DOUT[7] / LCD_D[7] / UPP_XD[15]] / GP7[15] / PRU1_R31[15] U2 O CP[28] C
VP_DOUT[6] / LCD_D[6] / UPP_XD[14] / GP7[14] / PRU1_R31[14] U1 O CP[28] C
VP_DOUT[5] / LCD_D[5] / UPP_XD[13] / GP7[13] / PRU1_R31[13] V3 O CP[28] C
VP_DOUT[4] / LCD_D[4] / UPP_XD[12] / GP7[12] / PRU1_R31[12] V2 O CP[28] C
VP_DOUT[3] / LCD_D[3] / UPP_XD[11] / GP7[11] / PRU1_R31[11] V1 O CP[28] C
VP_DOUT[2] / LCD_D[2] / UPP_XD[10] / GP7[10] / PRU1_R31[10] W3 O CP[28] C
VP_DOUT[1] / LCD_D[1] / UPP_XD[9] / GP7[9] / PRU1_R31[9] W2 O CP[28] C
VP_DOUT[0] /LCD_D[0] / UPP_XD[8] / GP7[8] / PRU1_R31[8] W1 O CP[28] C
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