Datasheet

1
7
MDCLK
MDIO
(output)
1
4
5
MDCLK
MDIO
(input)
3
3
AM1808
SPRS653E –FEBRUARY 2010–REVISED MARCH 2014 www.ti.com
6.23.2 Management Data Input/Output (MDIO) Electrical Data/Timing
Table 6-101. Timing Requirements for MDIO Input (see Figure 6-50 and Figure 6-51)
1.3V, 1.2V, 1.1V 1.0V
NO. UNIT
MIN MAX MIN MAX
1 t
c(MDCLK)
Cycle time, MDCLK 400 400 ns
2 t
w(MDCLK)
Pulse duration, MDCLK high/low 180 180 ns
3 t
t(MDCLK)
Transition time, MDCLK 5 5 ns
4 t
su(MDIO-MDCLKH)
Setup time, MDIO data input valid before MDCLK high 16 21 ns
5 t
h(MDCLKH-MDIO)
Hold time, MDIO data input valid after MDCLK high 0 0 ns
Figure 6-50. MDIO Input Timing
Table 6-102. Switching Characteristics Over Recommended Operating Conditions for MDIO Output
(see Figure 6-51)
1.3V, 1.2V, 1.1V,
1.0V
NO. UNIT
MIN MAX
7 t
d(MDCLKL-MDIO)
Delay time, MDCLK low to MDIO data output valid 0 100 ns
Figure 6-51. MDIO Output Timing
194 Peripheral Information and Electrical Specifications Copyright © 2010–2014, Texas Instruments Incorporated
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