Datasheet

MII_TXCLK
2
3
1
MII_RXCLK
2
3
1
AM1808
SPRS653E –FEBRUARY 2010–REVISED MARCH 2014 www.ti.com
Table 6-93. EMAC Control Module RAM
BYTE ADDRESS DESCRIPTION
0x01E2 0000 - 0x01E2 1FFF EMAC Local Buffer Descriptor Memory
6.22.2 EMAC Electrical Data/Timing
Table 6-94. Timing Requirements for MII_RXCLK (see Figure 6-45)
1.3V, 1.2V, 1.1V 1.0V
NO. 10 Mbps 100 Mbps 10 Mbps UNIT
MIN MAX MIN MAX MIN MAX
1 t
c(MII_RXCLK)
Cycle time, MII_RXCLK 400 40 400 ns
2 t
w(MII_RXCLKH)
Pulse duration, MII_RXCLK high 140 14 140 ns
3 t
w(MII_RXCLKL)
Pulse duration, MII_RXCLK low 140 14 140 ns
Figure 6-45. MII_RXCLK Timing (EMAC - Receive)
Table 6-95. Timing Requirements for MII_TXCLK (see Figure 6-46)
1.3V, 1.2V, 1.1V 1.0V
NO. 10 Mbps 100 Mbps 10 Mbps UNIT
MIN MAX MIN MAX MIN MAX
1 t
c(MII_TXCLK)
Cycle time, MII_TXCLK 400 40 400 ns
2 t
w(MII_TXCLKH)
Pulse duration, MII_TXCLK high 140 14 140 ns
3 t
w(MII_TXCLKL)
Pulse duration, MII_TXCLK low 140 14 140 ns
Figure 6-46. MII_TXCLK Timing (EMAC - Transmit)
190 Peripheral Information and Electrical Specifications Copyright © 2010–2014, Texas Instruments Incorporated
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