Datasheet
J
H
G
F
E
D
C
B
A
10987654321
10987654321
EMA_D[15]/
GP3[7]
AXR15/
EPWM0TZ[0]/
ECAP2_APWM2/
GP0[7]
ACLKR/
PRU0_R30[20]/
GP0[15]/
PRU0_R31[22]
ACLKX/
PRU0_R30[19]/
GP0[14]/
PRU0_R31[21]
AHCLKX/
USB_REFCLKIN/
/
GP0[10]/
PRU0_R31[17]
UART1_CTS
AFSX/
GP0[12]/
PRU0_R31[19]
AFSR/
GP0[13]/
PRU0_R31[20]
AXR9/
DX1/
GP0[1]
AXR4/
FSR0/
GP1[12]/
MII_COL
AXR5/
CLKX0/
GP1[13]/
MII_TXCLK
AXR7/
EPWM1TZ[0]/
PRU0_R30[17]
GP1[15]/
PRU0_R31[7]
AXR10/
DR1/
GP0[2]
AXR1/
DX0/
GP1[9]/
MII_TXD[1]
AXR3/
FSX0/
GP1[11]/
MII_TXD[3]
AXR2/
DR0/
GP1[10]/
MII_TXD[2]
MMCSD1_DAT[6]/
LCD_MCLK/
PRU1_R30[6]/
GP8[10]/
PRU1_R31[7]
RTC_ALARM/
/
GP0[8]/
UART2_CTS
DEEPSLEEP
AXR0/
ECAP0_APWM0/
GP8[7]/
MII_TXD[0]/
CLKS0
PRU0_R30[24]/
MMCSD1_CLK/
UPP_CHB_START/
GP8[14]/
PRU1_R31[26]
MMCSD1_DAT[4]/
LCD_VSYNC/
PRU1_R30[4]/
GP8[8]/
PRU1_R31[5]
SATA_VSS
PRU0_R30[22]/
PRU1_R30[8]/
UPP_CHB_WAIT/
GP8[12]/
PRU1_R31[24]
AXR8/
CLKS1/
ECAP1_APWM1/
GP0[0]/
PRU0_R31[8]
AXR12/
FSR1/
GP0[4]
EMA_D[4]/
GP4[12]
AXR14/
CLKR1/
GP0[6]
EMA_WEN_DQM[1]/
GP2[2]
EMA_D[0]/
GP4[8]
EMA_A[19]/
MMCSD0_DAT[2]/
PRU1_R30[27]/
GP4[3]
EMA_D[9]/
GP3[1]
EMA_A_R /
GP3[9]
W
MMCSD0_CLK/
PRU1_R30[31]/
GP4[7]
EMA_D[8]/
GP3[0]
EMA_D[13]/
GP3[5]
VP_CLKIN2/
MMCSD1_DAT[3]/
PRU1_R30[3]/
GP6[4]/
PRU1_R31[4]
VP_CLKIN3/
MMCSD1_DAT[1]/
PRU1_R30[1]/
GP6[2]/
PRU1_R31[2]
AMUTE/
GP0[9]/
PRU0_R31[16]
PRU0_R30[16]/
UART2_RTS/
DV
DD3318_A
DV
DD3318_A
EMA_WE/
GP3[11]
EMA_D[10]/
GP3[2]
EMA_D[3]/
GP4[11]
EMA_SDCKE/
PRU0_R30[4]/
GP2[6]/
PRU0_R31[4]
EMA_D[14]/
GP3[6]
EMA_D[7]/
GP4[15]
EMA_D[1]/
GP4[9]
EMA_A[22]/
MMCSD0_CMD/
PRU1_R30[30]/
GP4[6]
EMA_D[2]/
GP4[10]
EMA_A[21]/
MMCSD0_DAT[0]/
PRU1_R30[29]/
GP4[5]
PRU0_R30[23]/
MMCSD1_CMD/
UPP_CHB_ENABLE/
GP8[13]/
PRU1_R31[25]
AHCLKR/
/
GP0[11]/
PRU0_R31[18]
PRU0_R30[18]/
UART1_RTS
EMA_D[12]/
GP3[4]
EMA_WEN_DQM[0]/
GP2[3]
EMA_CLK/
PRU0_R30[5]/
GP2[7]/
PRU0_R31[5]
AXR6/
CLKR0/
GP1[14]/
MII_TXEN/
PRU0_R31[6]
AXR11/
FSX1/
GP0[3]
EMA_D[6]/
GP4[14]
EMA_D[11]/
GP3[3]
RV
DD
EMA_D[5]/
GP4[13]
MMCSD1_DAT[7]/
LCD_PCLK/
PRU1_R30[7]/
GP8[11]
MMCSD1_DAT[5]/
LCD_HSYNC/
PRU1_R30[5]/
GP8[9]/
PRU1_R31[6]
PRU0_R30[25]/
MMCSD1_DAT[0]/
UPP_CHB_CLOCK/
GP8[15]/
PRU1_R31[27]
AXR13/
CLKX1/
GP0[5]
J
H
G
F
E
D
C
B
A
EMA_CS[4]/
GP3[13]
EMA_CAS/
PRU0_R30[2]/
GP2[4]/
PRU0_R31[2]
DV
DD3318_B
DV
DD3318_B
DV
DD3318_B
DV
DD3318_B
DV
DD18
CV
DD
CV
DD
DV
DD3318_B
DV
DD18
SATA_VSS
DV
DD3318_A
V
SS
V
SS
CV
DD
CV
DD
V
SS
V
SS
CV
DD
SATA_TXP
SATA_TXN
DV
DD3318_C
CV
DD
V
SS
V
SS
A B
CD
AM1808
www.ti.com
SPRS653E –FEBRUARY 2010–REVISED MARCH 2014
Figure 3-4. Pin Map (Quad D)
3.6 Pin Multiplexing Control
Device level pin multiplexing is controlled by registers PINMUX0 - PINMUX19 in the SYSCFG module.
For the device family, pin multiplexing can be controlled on a pin-by-pin basis. Each pin that is multiplexed
with several different functions has a corresponding 4-bit field in one of the PINMUX registers.
Pin multiplexing selects which of several peripheral pin functions controls the pin's IO buffer output data
and output enable values only. The default pin multiplexing control for almost every pin is to select 'none'
of the peripheral functions in which case the pin's IO buffer is held tri-stated.
Note that the input from each pin is always routed to all of the peripherals that share the pin; the PINMUX
registers have no effect on input from a pin.
Copyright © 2010–2014, Texas Instruments Incorporated Device Overview 17
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