Datasheet

AM1808
SPRS653E –FEBRUARY 2010–REVISED MARCH 2014 www.ti.com
Table 6-76. Additional
(1)
SPI1 Master Timings, 5-Pin Option
(2)(3)
1.3V, 1.2V 1.1V 1.0V
NO. PARAMETER UNIT
MIN MAX MIN MAX MIN MAX
Polarity = 0, Phase = 0,
0.5M+P+5 0.5M+P+5 0.5M+P+6
from SPI1_CLK falling
Polarity = 0, Phase = 1,
Max delay for slave to deassert
P+5 P+5 P+6
from SPI1_CLK falling
SPI1_ENA after final SPI1_CLK
18 t
d(SPC_ENA)M
ns
edge to ensure master does not
Polarity = 1, Phase = 0,
0.5M+P+5 0.5M+P+5 0.5M+P+6
begin the next transfer.
(4)
from SPI1_CLK rising
Polarity = 1, Phase = 1,
P+5 P+5 P+6
from SPI1_CLK rising
Polarity = 0, Phase = 0,
0.5M+P-1 0.5M+P-5 0.5M+P-6
from SPI1_CLK falling
Polarity = 0, Phase = 1,
P-1 P-5 P-6
from SPI1_CLK falling
Delay from final SPI1_CLK edge to
20 t
d(SPC_SCS)M
ns
master deasserting SPI1_SCS
(5)(6)
Polarity = 1, Phase = 0,
0.5M+P-1 0.5M+P-5 0.5M+P-6
from SPI1_CLK rising
Polarity = 1, Phase = 1,
P-1 P-5 P-6
from SPI1_CLK rising
Max delay for slave SPI to drive SPI1_ENA valid after master
21 t
d(SCSL_ENAL)M
asserts SPI1_SCS to delay the C2TDELAY+P C2TDELAY+P C2TDELAY+P ns
master from beginning the next transfer,
Polarity = 0, Phase = 0,
2P-1 2P-5 2P-6
to SPI1_CLK rising
Polarity = 0, Phase = 1,
0.5M+2P-1 0.5M+2P-5 0.5M+2P-6
to SPI1_CLK rising
Delay from SPI1_SCS active to first
22 t
d(SCS_SPC)M
ns
SPI1_CLK
(7)(8) (9)
Polarity = 1, Phase = 0,
2P-1 2P-5 2P-6
to SPI1_CLK falling
Polarity = 1, Phase = 1,
0.5M+2P-1 0.5M+2P-5 0.5M+2P-6
to SPI1_CLK falling
(1) These parameters are in addition to the general timings for SPI master modes (Table 6-73).
(2) P = SYSCLK2 period; M = t
c(SPC)M
(SPI master bit clock period)
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPI1_ENA deassertion.
(5) Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI1_SCS will remain asserted.
(6) This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].
(7) If SPI1_ENA is asserted immediately such that the transmission is not delayed by SPI1_ENA.
(8) In the case where the master SPI is ready with new data before SPI1_SCS assertion.
(9) This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].
164 Peripheral Information and Electrical Specifications Copyright © 2010–2014, Texas Instruments Incorporated
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