Datasheet

AM1808
www.ti.com SPRS653E –FEBRUARY 2010–REVISED MARCH 2014
Table 6-74. Additional
(1)
SPI1 Master Timings, 4-Pin Enable Option
(2)(3)
1.3V, 1.2V 1.1V 1.0V
NO. PARAMETER UNIT
MIN MAX MIN MAX MIN MAX
Polarity = 0, Phase = 0,
3P+5 3P+5 3P+6
to SPI1_CLK rising
Delay from slave
Polarity = 0, Phase = 1,
0.5M+3P+5 0.5M+3P+5 0.5M+3P+6
assertion of
to SPI1_CLK rising
17 t
d(EN A_SPC)M
SPI1_ENA active to ns
Polarity = 1, Phase = 0,
first SPI1_CLK from
3P+5 3P+5 3P+6
to SPI1_CLK falling
master.
(4)
Polarity = 1, Phase = 1,
0.5M+3P+5 0.5M+3P+5 0.5M+3P+6
to SPI1_CLK falling
Polarity = 0, Phase = 0,
0.5M+P+5 0.5M+P+5 0.5M+P+6
from SPI1_CLK falling
Max delay for slave to
Polarity = 0, Phase = 1,
deassert SPI1_ENA
P+5 P+5 P+6
from SPI1_CLK falling
after final SPI1_CLK
18 t
d(SPC_ENA)M
ns
edge to ensure
Polarity = 1, Phase = 0,
0.5M+P+5 0.5M+P+5 0.5M+P+6
master does not begin
from SPI1_CLK rising
the next transfer.
(5)
Polarity = 1, Phase = 1,
P+5 P+5 P+6
from SPI1_CLK rising
(1) These parameters are in addition to the general timings for SPI master modes (Table 6-72).
(2) P = SYSCLK2 period; M = t
c(SPC)M
(SPI master bit clock period)
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPI1_ENA assertion.
(5) In the case where the master SPI is ready with new data before SPI1_ENA deassertion.
Table 6-75. Additional
(1)
SPI1 Master Timings, 4-Pin Chip Select Option
(2) (3)
1.3V, 1.2V 1.1V 1.0V
NO. PARAMETER UNIT
MIN MAX MIN MAX MIN MAX
Polarity = 0, Phase = 0,
2P-1 2P-5 2P-6
to SPI1_CLK rising
Polarity = 0, Phase = 1,
Delay from
0.5M+2P-1 0.5M+2P-5 0.5M+2P-6
to SPI1_CLK rising
SPI1_SCS active
19 t
d(SCS_SPC)M
ns
to first
Polarity = 1, Phase = 0,
2P-1 2P-5 2P-6
SPI1_CLK
(4) (5)
to SPI1_CLK falling
Polarity = 1, Phase = 1,
0.5M+2P-1 0.5M+2P-5 0.5M+2P-6
to SPI1_CLK falling
Polarity = 0, Phase = 0,
0.5M+P-1 0.5M+P-5 0.5M+P-6
from SPI1_CLK falling
Delay from final
Polarity = 0, Phase = 1,
P-1 P-5 P-6
SPI1_CLK edge to
from SPI1_CLK falling
20 t
d(SPC_SCS)M
master ns
Polarity = 1, Phase = 0,
deasserting
0.5M+P-1 0.5M+P-5 0.5M+P-6
from SPI1_CLK rising
SPI1_SCS
(6) (7)
Polarity = 1, Phase = 1,
P-1 P-5 P-6
from SPI1_CLK rising
(1) These parameters are in addition to the general timings for SPI master modes (Table 6-72).
(2) P = SYSCLK2 period; M = t
c(SPC)M
(SPI master bit clock period)
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPI1_SCS assertion.
(5) This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].
(6) Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI1_SCS will remain
asserted.
(7) This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].
Copyright © 2010–2014, Texas Instruments Incorporated Peripheral Information and Electrical Specifications 163
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