Datasheet

AM1808
SPRS653E –FEBRUARY 2010–REVISED MARCH 2014 www.ti.com
Table 6-73. General Timing Requirements for SPI1 Slave Modes
(1)
1.3V, 1.2V 1.1V 1.0V
NO. UNIT
MIN MAX MIN MAX MIN MAX
9 t
c(SPC)S
Cycle Time, SPI1_CLK, All Slave Modes 40
(2)
50
(2)
60
(2)
ns
10 t
w(SPCH)S
Pulse Width High, SPI1_CLK, All Slave Modes 18 22 27 ns
11 t
w(SPCL)S
Pulse Width Low, SPI1_CLK, All Slave Modes 18 22 27 ns
Polarity = 0, Phase = 0,
2P 2P 2P
to SPI1_CLK rising
Polarity = 0, Phase = 1,
Setup time, transmit data
2P 2P 2P
to SPI1_CLK rising
written to SPI before initial
12 t
su(SOMI_SPC)S
ns
clock edge from
Polarity = 1, Phase = 0,
2P 2P 2P
master.
(3) (4)
to SPI1_CLK falling
Polarity = 1, Phase = 1,
2P 2P 2P
to SPI1_CLK falling
Polarity = 0, Phase = 0,
15 17 19
from SPI1_CLK rising
Polarity = 0, Phase = 1,
15 17 19
Delay, subsequent bits valid
from SPI1_CLK falling
13 t
d(SPC_SOMI)S
on SPI1_SOMI after transmit ns
Polarity = 1, Phase = 0,
edge of SPI1_CLK
15 17 19
from SPI1_CLK falling
Polarity = 1, Phase = 1,
15 17 19
from SPI1_CLK rising
Polarity = 0, Phase = 0,
0.5S-4 0.5S-10 0.5S-12
from SPI1_CLK falling
Polarity = 0, Phase = 1,
0.5S-4 0.5S-10 0.5S-12
Output hold time, SPI1_SOMI
from SPI1_CLK rising
14 t
oh(SPC_SOMI)S
valid after receive edge of ns
Polarity = 1, Phase = 0,
SPI1_CLK
0.5S-4 0.5S-10 0.5S-12
from SPI1_CLK rising
Polarity = 1, Phase = 1,
0.5S-4 0.5S-10 0.5S-12
from SPI1_CLK falling
Polarity = 0, Phase = 0,
1.5 1.5 1.5
to SPI1_CLK falling
Polarity = 0, Phase = 1,
1.5 1.5 1.5
Input Setup Time, SPI1_SIMO
to SPI1_CLK rising
15 t
su(SIMO_SPC)S
valid before receive edge of ns
Polarity = 1, Phase = 0,
SPI1_CLK
1.5 1.5 1.5
to SPI1_CLK rising
Polarity = 1, Phase = 1,
1.5 1.5 1.5
to SPI1_CLK falling
Polarity = 0, Phase = 0,
4 5 6
from SPI1_CLK falling
Polarity = 0, Phase = 1,
4 5 6
Input Hold Time, SPI1_SIMO
from SPI1_CLK rising
16 t
ih(SPC_SIMO)S
valid after receive edge of ns
Polarity = 1, Phase = 0,
SPI1_CLK
4 5 6
from SPI1_CLK rising
Polarity = 1, Phase = 1,
4 5 6
from SPI1_CLK falling
(1) P = SYSCLK2 period; S = t
c(SPC)S
(SPI slave bit clock period)
(2) This timing is limited by the timing shown or 3P, whichever is greater.
(3) First bit may be MSB or LSB depending upon SPI configuration. SO(0) refers to first bit and SO(n) refers to last bit output on
SPI1_SOMI. SI(0) refers to the first bit input and SI(n) refers to the last bit input on SPI1_SIMO.
(4) Measured from the termination of the write of new data to the SPI module, In analyzing throughput requirements, additional internal bus
cycles must be accounted for to allow data to be written to the SPI module by the CPU.
162 Peripheral Information and Electrical Specifications Copyright © 2010–2014, Texas Instruments Incorporated
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