Datasheet

AM1808
www.ti.com SPRS653E –FEBRUARY 2010–REVISED MARCH 2014
6.16.2 McBSP Electrical Data/Timing
The following assume testing over recommended operating conditions.
6.16.2.1 Multichannel Buffered Serial Port (McBSP) Timing
Table 6-53. Timing Requirements for McBSP0 [1.3V, 1.2V, 1.1V]
(1)
(see Figure 6-32)
1.3V, 1.2V 1.1V
NO. UNIT
MIN MAX MIN MAX
2 t
c(CKRX)
Cycle time, CLKR/X CLKR/X ext 2P or 20
(2)(3)
2P or 25
(2)(3)
ns
3 t
w(CKRX)
Pulse duration, CLKR/X high or CLKR/X low CLKR/X ext P - 1
(4)
P - 1
(4)
ns
CLKR int 14 15.5
Setup time, external FSR high before CLKR
5 t
su(FRH-CKRL)
ns
low
CLKR ext 4 5
CLKR int 6 6
6 t
h(CKRL-FRH)
Hold time, external FSR high after CLKR low ns
CLKR ext 3 3
CLKR int 14 15.5
7 t
su(DRV-CKRL)
Setup time, DR valid before CLKR low ns
CLKR ext 4 5
CLKR int 3 3
8 t
h(CKRL-DRV)
Hold time, DR valid after CLKR low ns
CLKR ext 3 3
CLKX int 14 15.5
Setup time, external FSX high before CLKX
10 t
su(FXH-CKXL)
ns
low
CLKX ext 4 5
CLKX int 6 6
11 t
h(CKXL-FXH)
Hold time, external FSX high after CLKX low ns
CLKX ext 3 3
(1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also
inverted.
(2) P = ASYNC3 period in ns. For example, when the ASYNC clock domain is running at 100 MHz, use 10 ns.
(3) Use whichever value is greater. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock
source. The minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA
limitations and AC timing requirements.
(4) This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.
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