Datasheet

AM1808
www.ti.com SPRS653E –FEBRUARY 2010–REVISED MARCH 2014
Table 6-47. McASP AFIFO Registers Accessed Through Peripheral Configuration Port
BYTE ADDRESS ACRONYM REGISTER DESCRIPTION
0x01D0 1000 AFIFOREV AFIFO revision identification register
0x01D0 1010 WFIFOCTL Write FIFO control register
0x01D0 1014 WFIFOSTS Write FIFO status register
0x01D0 1018 RFIFOCTL Read FIFO control register
0x01D0 101C RFIFOSTS Read FIFO status register
6.15.2 McASP Electrical Data/Timing
6.15.2.1 Multichannel Audio Serial Port 0 (McASP0) Timing
Table 6-48 and Table 6-50 assume testing over recommended operating conditions (see Figure 6-30 and
Figure 6-31).
Table 6-48. Timing Requirements for McASP0 (1.3V, 1.2V, 1.1V)
(1)(2)
1.3V, 1.2V 1.1V
NO. UNIT
MIN MAX MIN MAX
1 t
c(AHCLKRX)
Cycle time, AHCLKR/X 25 28 ns
2 t
w(AHCLKRX)
Pulse duration, AHCLKR/X high or low 12.5 14 ns
3 t
c(ACLKRX)
Cycle time, ACLKR/X AHCLKR/X ext 25
(3)
28
(3)
ns
4 t
w(ACLKRX)
Pulse duration, ACLKR/W high or low AHCLKR/X ext 12.5 14 ns
AHCLKR/X int 11.5 12 ns
Setup time,
5 t
su(AFSRX-ACLKRX)
AHCLKR/X ext input 4 5 ns
AFSR/X input to ACLKR/X
(4)
AHCLKR/X ext output 4 5 ns
AHCLKR/X int -1 -2 ns
Hold time,
6 t
h(ACLKRX-AFSRX)
AHCLKR/X ext input 1 1 ns
AFSR/X input after ACLKR/X
(4)
AHCLKR/X ext output 1 1 ns
AHCLKR/X int 11.5 12 ns
Setup time,
7 t
su(AXR-ACLKRX)
AXR0[n] input to ACLKR/X
(4)(5)
AHCLKR/X ext 4 5 ns
AHCLKR/X int -1 -2 ns
Hold time,
8 t
h(ACLKRX-AXR)
AHCLKR/X ext input 3 4 ns
AXR0[n] input after ACLKR/X
(4)(5)
AHCLKR/X ext output 3 4 ns
(1) ACLKX0 internal – McASP0 ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
ACLKX0 external input – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX0 external output – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
ACLKR0 internal – McASP0 ACLKRCTL.CLKRM = 1, PDIR.ACLKR =1
ACLKR0 external input – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR0 external output – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
(2) P = SYSCLK2 period
(3) This timing is limited by the timing shown or 2P, whichever is greater.
(4) McASP0 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR0
(5) McASP0 ACLKXCTL.ASYNC=0: Receiver is clocked by transmitter's ACLKX0
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