Datasheet

ReceiveLogic
C lo ck/Fra m e G e n e rato r
StateMachine
ClockCheckand
Serializer0
Serializer1
Serializery
GIO
Control
DITRAM
384C
384U
Optional
Tra n s m it
F o rm atter
Receive
F o rm atter
Tra n s m it L o g ic
C lo ck/Fra m e G e n e rato r
StateMachine
McASP
Peripheral
Configuration
Bus
McASP
DMA Bus
(Dedicated)
AHCLKRx
ACLKRx
AFSRx
AMUTEINx
AMUTEx
AFSXx
ACLKXx
AHCLKXx
AXRx[0]
AXRx[1]
AXRx[y]
Pins
Function
ReceiveMasterClock
ReceiveBitClock
R e c eive L e ft/Rig h t C loc k o r F ra m e S y n c
Tra n s m it M aste r C lock
Tra n s m it B it C lock
Tra n s m it L e ft/R igh t C lo ck o r F ram e S ync
Tra n s m it/R ec e ive S e rial D ata P in
Tra n s m it/R ec e ive S e rial D ata P in
Tra n s m it/R ec e ive S e rial D ata P in
ErrorDetection
TheMcASP DOESNOThavea
dedicated AMUTEINpin.
AM1808
www.ti.com SPRS653E –FEBRUARY 2010–REVISED MARCH 2014
6.15 Multichannel Audio Serial Port (McASP)
The McASP serial port is specifically designed for multichannel audio applications. Its key features are:
• Flexible clock and frame sync generation logic and on-chip dividers
• Up to sixteen transmit or receive data pins and serializers
• Large number of serial data format options, including:
– TDM Frames with 2 to 32 time slots per frame (periodic) or 1 slot per frame (burst)
– Time slots of 8,12,16, 20, 24, 28, and 32 bits
– First bit delay 0, 1, or 2 clocks
– MSB or LSB first bit order
– Left- or right-aligned data words within time slots
• DIT Mode with 384-bit Channel Status and 384-bit User Data registers
• Extensive error checking and mute generation logic
• All unused pins GPIO-capable
• Transmit & Receive FIFO Buffers allow the McASP to operate at a higher sample rate by making it
more tolerant to DMA latency.
• Dynamic Adjustment of Clock Dividers
– Clock Divider Value may be changed without resetting the McASP
Figure 6-29. McASP Block Diagram
Copyright © 2010–2014, Texas Instruments Incorporated Peripheral Information and Electrical Specifications 133
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