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AM1808

SPRS653E –FEBRUARY 2010–REVISED MARCH 2014

AM1808 ARM

Microprocessor

1 AM1808 ARM Microprocessor

1.1 Features

• 375- and 456-MHz ARM926EJ-S™ RISC MPU • Programmable Real-Time Unit Subsystem

(PRUSS)

• ARM926EJ-S Core

– Two Independent Programmable Real-Time Unit

– 32-Bit and 16-Bit ( Thumb

) Instructions

(PRU) Cores

– Single-Cycle MAC

• 32-Bit Load-Store RISC Architecture

– ARM Jazelle

Technology

• 4KB of Instruction RAM per Core

– Embedded ICE-RT™ for Real-Time Debug

• 512 Bytes of Data RAM per Core

• ARM9™ Memory Architecture

• PRUSS can be Disabled via Software to

– 16KB of Instruction Cache

Save Power

– 16KB of Data Cache

• Register 30 of Each PRU is Exported from

– 8KB of RAM (Vector Table)

the Subsystem in Addition to the Normal R31

– 64KB of ROM

Output of the PRU Cores.

• Enhanced Direct Memory Access Controller 3

– Standard Power-Management Mechanism

(EDMA3):

• Clock Gating

– 2 Channel Controllers

• Entire Subsystem Under a Single PSC Clock

– 3 Transfer Controllers

Gating Domain

– 64 Independent DMA Channels

– Dedicated Interrupt Controller

– 16 Quick DMA Channels

– Dedicated Switched Central Resource

– Programmable Transfer Burst Size

• USB 1.1 OHCI (Host) with Integrated PHY (USB1)

• 128KB of On-Chip Memory

• USB 2.0 OTG Port with Integrated PHY (USB0)

• 1.8-V or 3.3-V LVCMOS I/Os (Except for USB and

– USB 2.0 High- and Full-Speed Client

DDR2 Interfaces)

– USB 2.0 High-, Full-, and Low-Speed Host

• Two External Memory Interfaces:

– End Point 0 (Control)

– EMIFA

– End Points 1,2,3,4 (Control, Bulk, Interrupt or

• NOR (8- or 16-Bit-Wide Data)

ISOC) RX and TX

• NAND (8- or 16-Bit-Wide Data)

• One Multichannel Audio Serial Port (McASP):

• 16-Bit SDRAM with 128-MB Address Space

– Transmit and Receive Clocks

– DDR2/Mobile DDR Memory Controller with one

– Two Clock Zones and 16 Serial Data Pins

of the following:

– Supports TDM, I2S, and Similar Formats

• 16-Bit DDR2 SDRAM with 256-MB Address

– DIT-Capable

Space

– FIFO Buffers for Transmit and Receive

• 16-Bit mDDR SDRAM with 256-MB Address

• Two Multichannel Buffered Serial Ports (McBSPs):

Space

– Transmit and Receive Clocks

• Three Configurable 16550-Type UART Modules:

– Supports TDM, I2S, and Similar Formats

– With Modem Control Signals

– AC97 Audio Codec Interface

– 16-Byte FIFO

– Telecom Interfaces (ST-Bus, H100)

– 16x or 13x Oversampling Option

– 128-Channel TDM

• LCD Controller

– FIFO Buffers for Transmit and Receive

• Two Serial Peripheral Interfaces (SPIs) Each with

• 10/100 Mbps Ethernet MAC (EMAC):

Multiple Chip Selects

– IEEE 802.3 Compliant

• Two Multimedia Card (MMC)/Secure Digital (SD)

Card Interfaces with Secure Data I/O (SDIO)

– MII Media-Independent Interface

Interfaces

– RMII Reduced Media-Independent Interface

• Two Master and Slave Inter-Integrated Circuits

– Management Data I/O (MDIO) Module

( I

C Bus™)

• One Host-Port Interface (HPI) with 16-Bit-Wide

Muxed Address and Data Bus For High Bandwidth

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

Summary of content (264 pages)

PAGE 1
Product Folder Sample & Buy Technical Documents Tools & Software Support & Community AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 AM1808 ARM® Microprocessor 1 AM1808 ARM Microprocessor 1.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com • Video Port Interface (VPIF): – Two 8-Bit SD (BT.656), Single 16-Bit or Single Raw (8-, 10-, and 12-Bit) Video Capture Channels – Two 8-Bit SD (BT.
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AM1808 www.ti.com 1.3 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 Description The AM1808 ARM Microprocessor is a low-power applications processor based on ARM926EJ-S. The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance life through the maximum flexibility of a fully integrated mixed processor solution.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 1.4 www.ti.com Functional Block Diagram Figure 1-1 shows the functional block diagram of the device.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 Table of Contents 1 2 3 1 6.10 External Memory Interface A (EMIFA) .............. 98 1.1 Features .............................................. 1 6.11 DDR2/mDDR Memory Controller .................. 109 1.2 Applications ........................................... 2 6.12 Memory Protection Units 1.3 Description ............................................ 3 6.13 MMC / SD / SDIO (MMCSD0, MMCSD1) 1.4 Functional Block Diagram ...
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com 2 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. This data manual revision history highlights the changes made to the SPRS653D device-specific data manual to make it an SPRS653E revision.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 3 Device Overview 3.1 Device Characteristics Table 3-1 provides an overview of the device. The table shows significant features of the device, including the capacity of on-chip RAM, peripherals, and the package type with pin count. Table 3-1.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 3.2 www.ti.com Device Compatibility The ARM926EJ-S RISC CPU is compatible with other ARM9 CPUs from ARM Holdings plc. 3.
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AM1808 www.ti.com 3.3.3 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 MMU A single set of two level page tables stored in main memory is used to control the address translation, permission checks and memory region attributes for both data and instruction accesses. The MMU uses a single unified Translation Lookaside Buffer (TLB) to cache the information held in the page tables. The MMU features are: • Standard ARM architecture v4 and v5 MMU mapping sizes, domains and access protection scheme.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 3.3.6 www.ti.com Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB) To support real-time trace, the ARM926EJ-S processor provides an interface to enable connection of an Embedded Trace Macrocell (ETM). The ARM926ES-J Subsystem in the device also includes the Embedded Trace Buffer (ETB). The ETM consists of two parts: • Trace Port provides real-time trace capability for the ARM9.
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AM1808 www.ti.com 3.4 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 Memory Map Summary Note: Read/Write accesses to illegal or reserved addresses in the memory map may cause undefined behavior. Table 3-2.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com Table 3-2.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 Table 3-2.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 3.5 www.ti.com Pin Assignments Extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions in the smallest possible package. Pin multiplexing is controlled using a combination of hardware configuration at device reset and software programmable register settings. 3.5.1 Pin Map (Bottom View) The following graphics show the bottom view of the ZCE and ZWT packages pin assignments in four quadrants (A, B, C, and D).
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AM1808 www.ti.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 A B D C www.ti.
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AM1808 www.ti.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 3.7 www.ti.com Terminal Functions Table 3-3 to Table 3-29 identify the external signal names, the associated pin/ball numbers along with the mechanical package designator, the pin type (I, O, IO, OZ, or PWR), whether the pin/ball has any internal pullup/pulldown resistors, whether the pin/ball is configurable as an IO in GPIO mode, and a functional pin description. 3.7.1 Device Reset and JTAG Table 3-3.
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AM1808 www.ti.com 3.7.2 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 High-Frequency Oscillator and PLL Table 3-4. High-Frequency Oscillator and PLL Terminal Functions SIGNAL NAME CLKOUT / UHPI_HDS2 / PRU1_R30[13] / GP6[14] NO. T18 TYPE (1) PULL (2) POWER GROUP (3) O CP[22] C DESCRIPTION PLL Observation Clock 1.2-V OSCILLATOR OSCIN L19 I — — Oscillator input OSCOUT K19 O — — Oscillator output OSCVSS L18 GND — — Oscillator ground PLL0_VDDA L15 PWR — — PLL analog VDD (1.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 3.7.3 www.ti.com Real-Time Clock and 32-kHz Oscillator Table 3-5. Real-Time Clock (RTC) and 1.2-V, 32-kHz Oscillator Terminal Functions SIGNAL NAME NO.
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AM1808 www.ti.com 3.7.5 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 External Memory Interface A (EMIFA) Table 3-7. External Memory Interface A (EMIFA) Terminal Functions SIGNAL NAME NO.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com Table 3-7. External Memory Interface A (EMIFA) Terminal Functions (continued) SIGNAL NAME NO.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 Table 3-7. External Memory Interface A (EMIFA) Terminal Functions (continued) SIGNAL NAME NO.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 3.7.6 www.ti.com DDR2/mDDR Memory Controller Table 3-8. DDR2/mDDR Terminal Functions SIGNAL NAME NO.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 Table 3-8. DDR2/mDDR Terminal Functions (continued) SIGNAL NAME NO. TYPE (1) PULL (2) DESCRIPTION DDR_DQM[0] W13 O IPD DDR_DQM[1] R10 O IPD DDR_DQS[0] T14 I/O IPD DDR_DQS[1] V11 I/O IPD DDR_BA[2] U8 O IPD DDR_BA[1] T9 O IPD DDR_BA[0] V8 O IPD DDR_DQGATE0 R11 O IPD DDR2 loopback signal for external DQS gating. Route to DDR and back to DDR_DQGATE1 with same constraints as used for DDR clock and data.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 3.7.7 www.ti.com Serial Peripheral Interface Modules (SPI) Table 3-9. Serial Peripheral Interface (SPI) Terminal Functions SIGNAL NAME NO.
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AM1808 www.ti.com 3.7.8 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 Programmable Real-Time Unit (PRU) Table 3-10. Programmable Real-Time Unit (PRU) Terminal Functions SIGNAL NAME NO.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com Table 3-10. Programmable Real-Time Unit (PRU) Terminal Functions (continued) SIGNAL NAME NO.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 Table 3-10. Programmable Real-Time Unit (PRU) Terminal Functions (continued) SIGNAL NAME NO.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com Table 3-10. Programmable Real-Time Unit (PRU) Terminal Functions (continued) SIGNAL NAME NO.
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AM1808 www.ti.com 3.7.9 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 Enhanced Capture/Auxiliary PWM Modules (eCAP0) The eCAP Module pins function as either input captures or auxiliary PWM 32-bit outputs, depending upon how the eCAP module is programmed. Table 3-11. Enhanced Capture Module (eCAP) Terminal Functions SIGNAL NAME NO.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 3.7.10 www.ti.com Enhanced Pulse Width Modulators (eHRPWM) Table 3-12. Enhanced Pulse Width Modulator (eHRPWM) Terminal Functions SIGNAL NAME NO.
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AM1808 www.ti.com 3.7.11 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 Boot Table 3-13. Boot Mode Selection Terminal Functions (1) SIGNAL NAME NO.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com 3.7.12 Universal Asynchronous Receiver/Transmitters (UART0, UART1, UART2) Table 3-14. Universal Asynchronous Receiver/Transmitter (UART) Terminal Functions SIGNAL NAME NO.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 3.7.13 Inter-Integrated Circuit Modules(I2C0, I2C1) Table 3-15. Inter-Integrated Circuit (I2C) Terminal Functions SIGNAL NAME NO.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com 3.7.14 Timers Table 3-16. Timers Terminal Functions SIGNAL NAME NO.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 3.7.15 Multichannel Audio Serial Ports (McASP) Table 3-17. Multichannel Audio Serial Ports Terminal Functions SIGNAL NAME NO.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com 3.7.16 Multichannel Buffered Serial Ports (McBSP) Table 3-18. Multichannel Buffered Serial Ports (McBSPs) Terminal Functions SIGNAL NAME NO.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 3.7.17 Universal Serial Bus Modules (USB0, USB1) Table 3-19. Universal Serial Bus (USB) Terminal Functions SIGNAL NAME NO. TYPE (1) PULL (2) POWER GROUP (3) DESCRIPTION USB0 2.0 OTG (USB0) USB0_DM M18 A IPD — USB0 PHY data minus USB0_DP M19 A IPD — USB0 PHY data plus USB0_VDDA33 N18 PWR — — USB0 PHY 3.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com 3.7.18 Ethernet Media Access Controller (EMAC) Table 3-20. Ethernet Media Access Controller (EMAC) Terminal Functions SIGNAL NAME NO.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 Table 3-20. Ethernet Media Access Controller (EMAC) Terminal Functions (continued) SIGNAL NAME NO.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com 3.7.19 Multimedia Card/Secure Digital (MMC/SD) Table 3-21. Multimedia Card/Secure Digital (MMC/SD) Terminal Functions SIGNAL NAME NO.
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AM1808 www.ti.com 3.7.20 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 Liquid Crystal Display Controller(LCD) Table 3-22. Liquid Crystal Display Controller (LCD) Terminal Functions SIGNAL NAME NO.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com 3.7.21 Serial ATA Controller (SATA) Table 3-23. Serial ATA Controller (SATA) Terminal Functions SIGNAL NAME NO.
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AM1808 www.ti.com 3.7.22 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 Universal Host-Port Interface (UHPI) Table 3-24. Universal Host-Port Interface (UHPI) Terminal Functions SIGNAL NAME NO.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com Table 3-24. Universal Host-Port Interface (UHPI) Terminal Functions (continued) SIGNAL NAME NO.
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AM1808 www.ti.com 3.7.23 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 Universal Parallel Port (uPP) Table 3-25.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com Table 3-25. Universal Parallel Port (uPP) Terminal Functions (continued) SIGNAL NAME NO.
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AM1808 www.ti.com 3.7.24 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 Video Port Interface (VPIF) Table 3-26. Video Port Interface (VPIF) Terminal Functions SIGNAL NAME NO.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com Table 3-26. Video Port Interface (VPIF) Terminal Functions (continued) SIGNAL NAME NO.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 3.7.25 General Purpose Input Output Table 3-27. General Purpose Input Output Terminal Functions SIGNAL NAME NO.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com Table 3-27. General Purpose Input Output Terminal Functions (continued) SIGNAL NAME NO.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 Table 3-27. General Purpose Input Output Terminal Functions (continued) SIGNAL NAME NO.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com Table 3-27. General Purpose Input Output Terminal Functions (continued) SIGNAL NAME NO.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 Table 3-27. General Purpose Input Output Terminal Functions (continued) SIGNAL NAME NO.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com 3.7.26 Reserved and No Connect Table 3-28. Reserved and No Connect Terminal Functions SIGNAL NAME NO. TYPE (1) DESCRIPTION Reserved. For proper device operation, this pin must be tied either directly to CVDD or left unconnected (do not connect to ground). RSV2 T19 PWR RSVDN J17 I NC M14, N16 — These pins may be left unconnected or connected to ground (VSS).
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 3.7.27 Supply and Ground Table 3-29. Supply and Ground Terminal Functions SIGNAL NAME TYPE (1) NO. DESCRIPTION CVDD (Core supply) E15, G7, G8, G13, H6, H7, H10, H11, H12, H13, J6, J12, K6, K12, L12, M8, M9, N8 PWR Variable (1.2V - 1.0V) core supply voltage pins RVDD (Internal RAM supply) E5, H14, N7 PWR 1.2V internal ram supply voltage pins DVDD18 (I/O supply) F14, G6, G10, G11, G12, J13, K5, L6, P13, R13 PWR 1.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 3.8 www.ti.com Unused Pin Configurations All signals multiplexed with multiple functions may be used as an alternate function if a given peripheral is not used. Unused non-multiplexed signals and some other specific signals should be handled as specified in the tables below. If NMI is unused, it should be pulled-high externally through a 10k-ohm resistor to supply DVDD3318_B. Table 3-30.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 Table 3-32. Unused RTC Signal Configuration (continued) SIGNAL NAME Configuration RTC_VSS VSS Table 3-33.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com 4 Device Configuration 4.1 Boot Modes This device supports a variety of boot modes through an internal ARM ROM bootloader. This device does not support dedicated hardware boot modes. The input states of the BOOT pins are sampled and latched into the BOOTCFG register, which is part of the system configuration (SYSCFG) module, when device reset is deasserted. Boot mode selection is determined by the values of the BOOT pins.
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AM1808 www.ti.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com Table 4-1.
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AM1808 www.ti.com 4.3 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 Pullup/Pulldown Resistors Proper board design should ensure that input pins to the device always be at a valid logic level and not floating. This may be achieved via pullup/pulldown resistors. The device features internal pullup (IPU) and internal pulldown (IPD) resistors on most pins to eliminate the need, unless otherwise noted, for external pullup/pulldown resistors.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com 5 Specifications 5.1 Absolute Maximum Ratings Over Operating Junction Temperature Range (Unless Otherwise Noted) (1) Core Logic, Variable and Fixed (CVDD, RVDD, RTC_CVDD, PLL0_VDDA , PLL1_VDDA , SATA_VDD, USB_CVDD ) (2) -0.5 V to 1.4 V I/O, 1.8V (USB0_VDDA18, USB1_VDDA18, SATA_VDDR, DDR_DVDD18) Supply voltage ranges -0.5 V to 2 V (2) I/O, 3.
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AM1808 www.ti.com 5.3 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 Recommended Operating Conditions NAME CVDD RVDD (1) NOM MAX UNIT 1.3 1.35 V 1.2V operating point 1.14 1.2 1.32 V 1.1V operating point 1.05 1.1 1.16 V 1.0V operating point 0.95 1.0 1.05 V 456 MHz versions 1.25 1.3 1.35 375 MHz versions 1.14 1.2 1.32 0.9 1.2 1.32 V PLL0 Supply Voltage 1.14 1.2 1.32 V PLL1_VDDA PLL1 Supply Voltage 1.14 1.2 1.32 V SATA_VDD SATA Core Logic Supply Voltage 1.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com Recommended Operating Conditions (continued) NAME USB USB0_VBUS Differential Clock Input Voltage Transition Time MAX UNIT Low-level input voltage, RTC_XI DESCRIPTION 0.2*RTC_CVDD V Low-level input voltage, OSCIN 0.2*CVDD V 0 5.
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AM1808 www.ti.com 5.4 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 Notes on Recommended Power-On Hours (POH) The information in the section below is provided solely for your convenience and does not extend or modify the warranty provided under TI’s standard terms and conditions for TI semiconductor products. To avoid significant degradation, the device power-on hours (POH) must be limited to the following: Table 5-1.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 5.5 www.ti.com Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Junction Temperature (Unless Otherwise Noted) PARAMETER High-level output voltage (dual-voltage LVCMOS IOs at 3.3V) (1) VOH High-level output voltage (dual-voltage LVCMOS IOs at 1.8V) (1) Low-level output voltage (dual-voltage LVCMOS I/Os at 3.3V) VOL Low-level output voltage (dual-voltage LVCMOS I/Os at 1.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 6 Peripheral Information and Electrical Specifications 6.1 Parameter Information 6.1.1 Parameter Information Device-Specific Information Tester Pin Electronics 42 Ω 3.5 nH Transmission Line Z0 = 50 Ω (see note) 4.0 pF A. 1.85 pF Data Sheet Timing Reference Point Output Under Test Device Pin (see note) The data sheet provides timing at the device pin.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 6.2 www.ti.com Recommended Clock and Control Signal Transition Behavior All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic manner. 6.3 6.3.1 Power Supplies Power-On Sequence The device should be powered-on in the following order: 1. RTC (RTC_CVDD) may be powered from an external device (such as a battery) prior to all other supplies being applied or powered-up at the same time as CVDD.
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AM1808 www.ti.com 6.4 6.4.1 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 Reset Power-On Reset (POR) A power-on reset (POR) is required to place the device in a known good state after power-up. Power-On Reset is initiated by bringing RESET and TRST low at the same time. POR sets all of the device internal logic to its default state. All pins are tri-stated with the exception of RESETOUT which remains active through the reset sequence, and RTCK/GP8[0].
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 • • • • 72 www.ti.com Internal memory is maintained through a warm reset RESETOUT goes active All device pins go to a high-impedance state The RTC peripheral is not reset during a warm reset.
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AM1808 www.ti.com 6.4.3 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 Reset Electrical Data Timings Table 6-1 assumes testing over the recommended operating conditions. Table 6-1. Reset Timing Requirements ( (1), (2) ) 1.3V, 1.2V NO. MIN MAX 1.1V MIN 1.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com Power Supplies Stable OSCIN TRST 1 RESET 5 4 RESETOUT 3 2 Boot Pins Driven or Hi-Z Config Figure 6-5.
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AM1808 www.ti.com 6.5 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 Crystal Oscillator or External Clock Input The device includes two choices to provide an external clock input, which is fed to the on-chip PLLs to generate high-frequency system clocks. These options are illustrated in Figure 6-6 and Figure 6-7. For input clock frequencies between 12 and 20 MHz, a crystal with 80 ohm max ESR is recommended. For input clock frequencies between 20 and 30 MHz, a crystal with 60 ohm max ESR is recommended.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com Clock Input to PLL OSCIN NC OSCOUT OSCVSS Figure 6-7. External 1.2V Clock Source Table 6-3. OSCIN Timing Requirements for an Externally Driven Clock MIN MAX UNIT fOSCIN OSCIN frequency range 12 50 MHz tc(OSCIN) Cycle time, external clock driven on OSCIN 20 ns tw(OSCINH) Pulse width high, external clock on OSCIN 0.4 tc(OSCIN) ns tw(OSCINL) Pulse width low, external clock on OSCIN 0.
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AM1808 www.ti.com 6.6.1 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 PLL Device-Specific Information The PLL requires some external filtering components to reduce power supply noise as shown in Figure 68. 1.14V - 1.32V PLL0_VDDA 50R 0.1 µF 0.01 µF VSS 50R PLL0_VSSA 1.14V - 1.32V 50R PLL1_VDDA 0.1 µF VSS 50R 0.01 µF PLL1_VSSA Ferrite Bead: Murata BLM31PG500SN1L or Equivalent Figure 6-8.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com PLL Controller 0 PLLCTL[EXTCLKSRC] PLL1_SYSCLK3 PLLCTL[CLKMODE] 1 PLLCTL[PLLEN] 0 OSCIN 0 Square Wave 1 Crystal 0 PREDIV POSTDIV PLL 1 PLLM DEEPSLEEP Enable PLLDIV1 (/1) SYSCLK1 PLLDIV2 (/2) SYSCLK2 PLLDIV4 (/4) SYSCLK4 PLLDIV5 (/3) SYSCLK5 PLLDIV6 (/1) SYSCLK6 PLLDIV7 (/6) SYSCLK7 PLLDIV3 (/3) SYSCLK3 EMIFA Internal Clock Source 0 1 DIV4.5 CFGCHIP3[EMA_CLKSRC] AUXCLK PLLC0 OBSCLK (CLKOUT Pin) DIV4.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 Table 6-4. Allowed PLL Operating Conditions (PLL0 and PLL1) NO .
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com The maximum voltage slew rate for CVdd supply changes is 1 mV/us. For additional information on power management solutions from TI for this processor, follow the Power Management link in the Product Folder on www.ti.com for this processor. The processor supports multiple clock domains some of which have clock ratio requirements to each other.
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AM1808 www.ti.com 6.7 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 Interrupts 6.7.1 ARM CPU Interrupts The ARM9 CPU core supports 2 direct interrupts: FIQ and IRQ. The ARM Interrupt Controller (AINTC) extends the number of interrupts to 100, and provides features like programmable masking, priority, hardware nesting support, and interrupt vector generation. 6.7.1.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 6.7.1.4 www.ti.com AINTC System Interrupt Assignments Table 6-6.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 Table 6-6.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com Table 6-6.
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AM1808 www.ti.com 6.7.1.5 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 AINTC Memory Map Table 6-7.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com Table 6-7.
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AM1808 www.ti.com 6.8 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 Power and Sleep Controller (PSC) The Power and Sleep Controllers (PSC) are responsible for managing transitions of system power on/off, clock on/off, resets (device level and module level). It is used primarily to provide granular power control for on chip modules (peripherals and CPU). A PSC module consists of a Global PSC (GPSC) and a set of Local PSCs (LPSCs).
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com Table 6-8.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 Table 6-8. Power and Sleep Controller (PSC) Registers (continued) PSC0 BYTE ADDRESS PSC1 BYTE ADDRESS ACRONYM - 0x01E2 7A74 MDCTL29 Module 29 Control Register - 0x01E2 7A78 MDCTL30 Module 30 Control Register - 0x01E2 7A7C MDCTL31 Module 31 Control Register 6.8.1 REGISTER DESCRIPTION Power Domain and Module Topology The device includes two PSC modules.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com PSC1 Default Module Configuration LPSC Number Module Name Power Domain Default Module State Auto Sleep/Wake Only 0 EDMA3 Channel Controller 1 AlwaysON (PD0) SwRstDisable — 1 USB0 (USB2.0) AlwaysON (PD0) SwRstDisable — 2 USB1 (USB1.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 Module States The PSC defines several possible states for a module. This states are essentially a combination of the module reset asserted or de-asserted and module clock on/enabled or off/disabled. The module states are defined in . Module States Module State Module Reset Module Clock Module State Definition Enable De-asserted On A module in the enable state has its module reset de-asserted and it has its clock on.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 6.9 www.ti.com EDMA The EDMA controller handles all data transfers between memories and the device slave peripherals on the device. These data transfers include cache servicing, non-cacheable memory accesses, userprogrammed data transfers, and host accesses. 6.9.1 EDMA3 Channel Synchronization Events Each EDMA channel controller supports up to 32 channels which service peripherals and memory.
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AM1808 www.ti.com 6.9.2 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 EDMA Peripheral Register Descriptions Table 6-10 is the list of EDMA3 Channel Controller Registers and Table 6-11 is the list of EDMA3 Transfer Controller registers. Table 6-10.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com Table 6-10.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 Table 6-10.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com Table 6-11.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 Table 6-12. EDMA Parameter Set RAM (continued) EDMA0 Channel Controller 0 BYTE ADDRESS RANGE EDMA1 Channel Controller 0 BYTE ADDRESS RANGE DESCRIPTION ... ... 0x01C0 4FC0 - 0x01C0 4FDF 0x01E3 4FC0 - 0x01E3 4FDF ... Parameters Set 126 (8 32-bit words) 0x01C0 4FE0 - 0x01C0 4FFF 0x01E3 4FE0 - 0x01E3 4FFF Parameters Set 127 (8 32-bit words) Table 6-13.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com 6.10 External Memory Interface A (EMIFA) EMIFA is one of two external memory interfaces supported on the device. It is primarily intended to support asynchronous memory types, such as NAND and NOR flash and Asynchronous SRAM. However on this device, EMIFA also provides a secondary interface to SDRAM. 6.10.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 Table 6-14.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com 6.10.4 External Memory Interface Register Descriptions Table 6-15.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 6.10.5 EMIFA Electrical Data/Timing Table 6-16 through Table 6-19 assume testing over recommended operating conditions. Table 6-16. Timing Requirements for EMIFA SDRAM Interface 1.3V, 1.2V NO. MIN 19 tsu(EMA_DV-EM_CLKH) Input setup time, read data valid on EMA_D[15:0] before EMA_CLK rising 20 th(CLKH-DIV) Input hold time, read data valid on EMA_D[15:0] after EMA_CLK rising MAX 1.1V MIN MAX 1.0V MIN MAX UNIT 2 3 3 ns 1.6 1.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com 1 BASIC SDRAM WRITE OPERATION 2 2 EMA_CLK 3 4 EMA_CS[0] 5 6 EMA_WE_DQM[1:0] 7 8 7 8 EMA_BA[1:0] EMA_A[12:0] 9 10 EMA_D[15:0] 11 12 EMA_RAS 13 EMA_CAS 15 16 EMA_WE Figure 6-10. EMIFA Basic SDRAM Write Operation BASIC SDRAM READ OPERATION 1 2 2 EMA_CLK 3 4 EMA_CS[0] 5 6 EMA_WE_DQM[1:0] 7 8 7 8 EMA_BA[1:0] EMA_A[12:0] 19 17 2 EM_CLK Delay 20 18 EMA_D[15:0] 11 12 EMA_RAS 13 14 EMA_CAS EMA_WE Figure 6-11.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 Table 6-18. Timing Requirements for EMIFA Asynchronous Memory Interface 1.2V NO. MIN MAX (1) 1.1V MIN MAX 1.0V MIN MAX UNIT READS and WRITES E tc(CLK) Cycle time, EMIFA module clock 2 tw(EM_WAIT) Pulse duration, EM_WAIT assertion and deassertion 6.75 13.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com Table 6-19. Switching Characteristics for EMIFA Asynchronous Memory Interface NO. (1) (2) (3) 1.3V, 1.2V, 1.1V, 1.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 Table 6-19. Switching Characteristics for EMIFA Asynchronous Memory Interface NO. (1) (2) (3) (continued) 1.3V, 1.2V, 1.1V, 1.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 SETUP www.ti.com STROBE HOLD 3 1 EMA_CS[5:2] EMA_BA[1:0] EMA_A[22:0] EMA_WE_DQM[1:0] 1 EMA_A_RW 4 8 6 28 5 9 7 29 10 EMA_OE 13 12 EMA_D[15:0] EMA_WE Figure 6-12.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 SETUP STROBE HOLD 15 1 EMA_CS[5:2] EMA_BA[1:0] EMA_A[22:0] EMA_WE_DQM[1:0] EMA_A_RW EMA_WE 16 17 18 19 20 21 22 30 23 31 24 26 1 27 EMA_D[15:0] EMA_OE Figure 6-13. Asynchronous Memory Write Timing for EMIFA EMA_CS[5:2] SETUP STROBE Extended Due to EMA_WAIT STROBE HOLD EMA_BA[1:0] EMA_A[22:0] EMA_D[15:0] EMA_A_RW 14 11 EMA_OE 2 EMA_WAIT Asserted 2 Deasserted Figure 6-14.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com EMA_CS[5:2] EMA_BA[1:0] EMA_A[22:0] EMA_D[15:0] EMA_A_RW EMA_WE EMA_WAIT Figure 6-15.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 6.11 DDR2/mDDR Memory Controller The DDR2/mDDR Memory Controller is a dedicated interface to DDR2/mDDR SDRAM. It supports JESD79-2A standard compliant DDR2 SDRAM devices and compliant Mobile DDR SDRAM devices.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com 6.11.
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AM1808 www.ti.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 6.11.3.2 Compatible JEDEC DDR2/mDDR Devices Table 6-21 shows the parameters of the JEDEC DDR2/mDDR devices that are compatible with this interface. Generally, the DDR2/mDDR interface is compatible with x16 DDR2-400/mDDR-200 speed grade DDR2/mDDR devices. The device also supports JEDEC DDR2/mDDR x8 devices in the dual chip configuration. In this case, one chip supplies the upper byte and the second chip supplies the lower byte.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com 6.11.3.4 Placement Figure 6-17 shows the required placement for the device as well as the DDR2/mDDR devices. The dimensions for Figure 6-18 are defined in Table 6-24. The placement does not restrict the side of the PCB that the devices are mounted on. The ultimate purpose of the placement is to limit the maximum trace lengths and allow for proper routing space.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 6.11.3.5 DDR2/mDDR Keep Out Region The region of the PCB used for the DDR2/mDDR circuitry must be isolated from other signals. The DDR2/mDDR keep out region is defined for this purpose and is shown in Figure 6-19. The size of this region varies with the placement and DDR routing. Additional clearances required for the keep out region are shown in Table 6-24.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com 6.11.3.6 Bulk Bypass Capacitors Bulk bypass capacitors are required for moderate speed bypassing of the DDR2/mDDR and other circuitry. Table 6-25 contains the minimum numbers and capacitance required for the bulk bypass capacitors. Note that this table only covers the bypass needs of the device and DDR2/mDDR interfaces. Additional bulk bypass capacitance may be needed for other circuitry. Table 6-25. Bulk Bypass Capacitors NO.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 6.11.3.8 Net Classes Table 6-27 lists the clock net classes for the DDR2/mDDR interface. Table 6-28 lists the signal net classes, and associated clock net classes, for the signals in the DDR2/mDDR interface. These net classes are used for the termination and routing rules that follow. Table 6-27. Clock Net Class Definitions CLOCK NET CLASS PIN NAMES CK DDR_CLKP / DDR_CLKN DQS0 DDR_DQS[0] DQS1 DDR_DQS[1] Table 6-28.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com 6.11.3.10 VREF Routing VREF is used as a reference by the input buffers of the DDR2/mDDR memories as well as the device. VREF is intended to be half the DDR2/mDDR power supply voltage and should be created using a resistive divider as shown in Figure 6-16. Other methods of creating VREF are not recommended. Figure 6-20 shows the layout guidelines for VREF.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 6.11.3.11 DDR2/mDDR CK and ADDR_CTRL Routing Figure 6-21 shows the topology of the routing for the CK and ADDR_CTRL net classes. The route is a balanced T as it is intended that the length of segments B and C be equal. In addition, the length of A should be maximized. B DDR2/mDDR Controller A1 T C A A1 Figure 6-21. CK and ADDR_CTRL Routing and Topology Table 6-30. CK and ADDR_CTRL Routing Specification NO.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com Figure 6-22 shows the topology and routing for the DQS and D net class; the routes are point to point. Skew matching across bytes is not needed nor recommended. E0 A1 T A1 DDR2/mDDR Controller T E1 Figure 6-22. DQS and D Routing and Topology Table 6-31. DQS and D Routing Specification NO.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 Figure 6-23 shows the routing for the DQGATE net class. Table 6-32 contains the routing specification. A1 T T DDR2/mDDR Controller F A1 Figure 6-23. DQGATE Routing Table 6-32. DQGATE Routing Specification NO.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com 6.12 Memory Protection Units The MPU performs memory protection checking. It receives requests from a bus master in the system and checks the address against the fixed and programmable regions to see if the access is allowed. If allowed, the transfer is passed unmodified to its output bus (to the targeted address).
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 Table 6-33. MPU1 Configuration Registers (continued) MPU1 BYTE ADDRESS ACRONYM 0x01E1 4300 FLTADDRR 0x01E1 4304 FLTSTAT Fault status 0x01E1 4308 FLTCLR Fault clear 0x01E1 430C - 0x01E1 4FFF - Reserved REGISTER DESCRIPTION Fault address Table 6-34.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com Table 6-34.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 6.13 MMC / SD / SDIO (MMCSD0, MMCSD1) 6.13.1 MMCSD Peripheral Description The device includes an two MMCSD controllers which are compliant with MMC V4.0, Secure Digital Part 1 Physical Layer Specification V1.1 and Secure Digital Input Output (SDIO) V2.0 specifications.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com 6.13.3 MMC/SD Electrical Data/Timing Table 6-36 through Table 6-37 assume testing over recommended operating conditions. Table 6-36. Timing Requirements for MMC/SD (see Figure 6-25 and Figure 6-27) 1.3V, 1.2V NO. 1 MIN tsu(CMDV- Setup time, MMCSD_CMD valid before MMCSD_CLK high MAX 1.1V MIN 1.0V MAX MIN MAX UNIT 4 4 6 ns CLKH) 2 th(CLKH-CMDV) 2.5 2.5 2.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 10 9 7 MMCSD_CLK 13 13 START MMCSD_CMD 13 XMIT Valid Valid 13 Valid END Figure 6-24. MMC/SD Host Command Timing 9 7 10 MMCSD_CLK 1 2 START MMCSD_CMD XMIT Valid Valid Valid END Figure 6-25. MMC/SD Card Response Timing 10 9 7 MMCSD_CLK 14 14 START MMCSD_DATx 14 D0 D1 14 Dx END Figure 6-26. MMC/SD Host Write Timing 9 10 7 MMCSD_CLK 4 4 3 MMCSD_DATx Start 3 D0 D1 Dx End Figure 6-27.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com 6.14 Serial ATA Controller (SATA) The Serial ATA Controller (SATA) provides a single HBA port operating in AHCI mode and is used to interface to data storage devices at both 1.5 Gbits/second and 3.0 Gbits/second line speeds.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 6.14.1 SATA Register Descriptions Table 6-38 is a list of the SATA Controller registers. Table 6-38.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com 6.14.2 SATA Interface This section provides the timing specification for the SATA interface as a PCB design and manufacturing specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk, and signal timing. TI has performed the simulation and system design work to ensure the SATA interface requirements are met. 6.14.2.1 SATA Interface Schematic Figure 6-28 shows the SATA interface schematic.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 6.14.2.2 PCB Stackup Specifications Table 6-40 shows the stackup and feature sizes required for SATA. Table 6-40.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com 6.14.2.5 SATA Interface Clock Source requirements A high-quality, low-jitter differential clock source is required for the SATA PHY. The SATA interface requires a LVDS differential clock source to be provided at signals SATA_REFCLKP and SATA_REFCLKN. The clock source should be placed physically as close to the processor as possible. Table 6-43 shows the requirements for the clock source. Table 6-43.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 6.15 Multichannel Audio Serial Port (McASP) The McASP serial port is specifically designed for multichannel audio applications.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com 6.15.1 McASP Peripheral Registers Description(s) Registers for the McASP are summarized in Table 6-45. The registers are accessed through the peripheral configuration port. The receive buffer registers (RBUF) and transmit buffer registers (XBUF) can also be accessed through the DMA port, as listed in Table 6-46 Registers for the McASP Audio FIFO (AFIFO) are summarized in Table 6-47.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 Table 6-45.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com Table 6-45.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 Table 6-47. McASP AFIFO Registers Accessed Through Peripheral Configuration Port BYTE ADDRESS ACRONYM REGISTER DESCRIPTION 0x01D0 1000 AFIFOREV AFIFO revision identification register 0x01D0 1010 WFIFOCTL Write FIFO control register 0x01D0 1014 WFIFOSTS Write FIFO status register 0x01D0 1018 RFIFOCTL Read FIFO control register 0x01D0 101C RFIFOSTS Read FIFO status register 6.15.2 McASP Electrical Data/Timing 6.15.2.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com Table 6-49. Timing Requirements for McASP0 (1.0V) (1) (2) 1.0V NO.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 Table 6-50. Switching Characteristics for McASP0 (1.3V, 1.2V, 1.1V) (1) NO. 9 tc(AHCLKRX) Cycle time, AHCLKR/X 10 tw(AHCLKRX) Pulse duration, AHCLKR/X high or low 11 tc(ACLKRX) Cycle time, ACLKR/X 12 tw(ACLKRX) Pulse duration, ACLKR/X high or low 13 td(ACLKRX-AFSRX) Delay time, ACLKR/X transmit edge to AFSX/R output valid (6) 14 td(ACLKX-AXRV) 15 (1) 1.3V, 1.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com 2 1 2 AHCLKR/X (Falling Edge Polarity) AHCLKR/X (Rising Edge Polarity) 4 3 4 ACLKR/X (CLKRP = CLKXP = 0)(A) ACLKR/X (CLKRP = CLKXP = 1)(B) 6 5 AFSR/X (Bit Width, 0 Bit Delay) AFSR/X (Bit Width, 1 Bit Delay) AFSR/X (Bit Width, 2 Bit Delay) AFSR/X (Slot Width, 0 Bit Delay) AFSR/X (Slot Width, 1 Bit Delay) AFSR/X (Slot Width, 2 Bit Delay) 8 7 AXR[n] (Data In/Receive) A. B.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 10 10 9 AHCLKR/X (Falling Edge Polarity) AHCLKR/X (Rising Edge Polarity) 12 11 12 ACLKR/X (CLKRP = CLKXP = 1)(A) ACLKR/X (CLKRP = CLKXP = 0)(B) 13 13 13 13 AFSR/X (Bit Width, 0 Bit Delay) AFSR/X (Bit Width, 1 Bit Delay) AFSR/X (Bit Width, 2 Bit Delay) 13 13 13 AFSR/X (Slot Width, 0 Bit Delay) AFSR/X (Slot Width, 1 Bit Delay) AFSR/X (Slot Width, 2 Bit Delay) 14 15 AXR[n] (Data Out/Transmit) A0 A. B.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com 6.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 6.16.2 McBSP Electrical Data/Timing The following assume testing over recommended operating conditions. 6.16.2.1 Multichannel Buffered Serial Port (McBSP) Timing Table 6-53. Timing Requirements for McBSP0 [1.3V, 1.2V, 1.1V] (1) (see Figure 6-32) 1.3V, 1.2V NO. MIN 1.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com Table 6-54. Timing Requirements for McBSP0 [1.0V] (1) (see Figure 6-32) 1.0V NO. MIN MAX UNIT 2 tc(CKRX) Cycle time, CLKR/X CLKR/X ext 2P or 26.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 Table 6-55. Switching Characteristics for McBSP0 [1.3V, 1.2V, 1.1V] (1) (2) (see Figure 6-32) NO. 1.3V, 1.2V PARAMETER MIN MAX 2 14.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com Table 6-56. Switching Characteristics for McBSP0 [1.0V] (1) (see Figure 6-32) NO. (2) 1.0V PARAMETER MIN MAX 3 21.5 1 td(CKSH-CKRXH) Delay time, CLKS high to CLKR/X high for internal CLKR/X generated from CLKS input 2 tc(CKRX) Cycle time, CLKR/X CLKR/X int 2P or 26.6 (3) (4) (5) 3 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X int C - 2 (6) C + 2 (6) CLKR int -4 10 CLKR ext 2.5 21.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 Table 6-57. Timing Requirements for McBSP1 [1.3V, 1.2V, 1.1V] (1) (see Figure 6-32) 1.3V, 1.2V NO.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com Table 6-59. Switching Characteristics for McBSP1 [1.3V, 1.2V, 1.1V] (1) (see Figure 6-32) NO. 1.3V, 1.2V PARAMETER MAX MIN MAX 0.5 16.5 1.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 Table 6-60. Switching Characteristics for McBSP1 [1.0V] (1) (see Figure 6-32) NO. tc(CKRX) Cycle time, CLKR/X CLKR/X int 2P or 26.6 (3) (4) (5) 3 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X int C - 2 (6) C + 2 (6) CLKR int -4 13 CLKR ext 2.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com CLKS 1 2 3 3 CLKR 4 4 FSR (int) 5 6 FSR (ext) 7 8 DR Bit(n1) (n2) (n3) 2 3 3 CLKX 9 FSX (int) 11 10 FSX (ext) FSX (XDATDLY=00b) DX A. 13 (A) 14 13 (A) Bit(n1) 12 Bit 0 (n2) (n3) No. 13 applies to the first data bit only when XDATDLY ≠ 0. Figure 6-32. McBSP Timing Table 6-61. Timing Requirements for McBSP0 FSR When GSYNC = 1 (see Figure 6-33) 1.3V, 1.2V NO. MIN 1.1V MAX MIN 1.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 6.17 Serial Peripheral Interface Ports (SPI0, SPI1) Figure 6-34 is a block diagram of the SPI module, which is a simple shift register and buffer plus control logic. Data is written to the shift register before transmission occurs and is read from the buffer at the end of transmission. The SPI can operate either as a master, in which case, it initiates a transfer and drives the SPIx_CLK pin, or as a slave.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com Optional − Slave Chip Select SPIx_SCS SPIx_SCS Optional Enable (Ready) SPIx_ENA SPIx_ENA SPIx_CLK SPIx_CLK SPIx_SOMI SPIx_SOMI SPIx_SIMO SPIx_SIMO MASTER SPI SLAVE SPI Figure 6-35.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 6.17.1 SPI Peripheral Registers Description(s) Table 6-63 is a list of the SPI registers. Table 6-63.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com 6.17.2 SPI Electrical Data/Timing 6.17.2.1 Serial Peripheral Interface (SPI) Timing Table 6-64 through Table 6-79 assume testing over recommended operating conditions (see Figure 6-36 through Figure 6-39). Table 6-64. General Timing Requirements for SPI0 Master Modes (1) 1.3V, 1.2V NO. 1.1V 1.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 Table 6-65. General Timing Requirements for SPI0 Slave Modes (1) 1.3V, 1.2V NO.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com Table 6-66. Additional SPI0 Master Timings, 4-Pin Enable Option NO. 17 td(ENA_SPC)M 18 (1) (2) (3) (4) (5) 1.3V, 1.2V PARAMETER td(SPC_ENA)M Delay from slave assertion of SPI0_ENA active to first SPI0_CLK from master. (4) Max delay for slave to deassert SPI0_ENA after final SPI0_CLK edge to ensure master does not begin the next transfer. (5) (1) (2) (3) MIN 1.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 Table 6-67. Additional SPI0 Master Timings, 4-Pin Chip Select Option NO. 20 (6) (7) 1.3V, 1.2V PARAMETER td(SPC_SCS)M MIN Delay from final SPI0_CLK edge to master deasserting SPI0_SCS (6) (7) (continued) 1.1V MAX MIN 1.0V MAX MIN MAX Polarity = 0, Phase = 0, from SPI0_CLK falling 0.5M+P-1 0.5M+P-2 0.5M+P-3 Polarity = 0, Phase = 1, from SPI0_CLK falling P-1 P-2 P-3 Polarity = 1, Phase = 0, from SPI0_CLK rising 0.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com Table 6-68. Additional SPI0 Master Timings, 5-Pin Option NO. 22 Delay from SPI0_SCS active to first SPI0_CLK (7) (8) (9) MIN td(ENA_SPC)M MIN MAX 2P-2 2P-3 Polarity = 0, Phase = 1, to SPI0_CLK rising 0.5M+2P-2 0.5M+2P-2 0.5M+2P-3 Polarity = 1, Phase = 0, to SPI0_CLK falling 2P-2 2P-2 2P-3 Polarity = 1, Phase = 1, to SPI0_CLK falling 0.5M+2P-2 0.5M+2P-2 0.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 Table 6-70. Additional SPI0 Slave Timings, 4-Pin Chip Select Option NO. 25 26 1.3V, 1.2V PARAMETER td(SCSL_SPC)S td(SPC_SCSH)S (1) (2) (3) MIN Required delay from SPI0_SCS asserted at slave to first SPI0_CLK edge at slave. Required delay from final SPI0_CLK edge before SPI0_SCS is deasserted. 1.1V MAX MIN 1.0V MAX MIN MAX P + 1.5 P + 1.5 P + 1.5 Polarity = 0, Phase = 0, from SPI0_CLK falling 0.5M+P+4 0.5M+P+4 0.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com Table 6-71. Additional SPI0 Slave Timings, 5-Pin Option NO. 30 (4) 160 Delay from final clock receive edge on SPI0_CLK to slave 3stating or driving high SPI0_ENA. (4) (continued) 1.3V, 1.2V PARAMETER tdis(SPC_ENA)S (1)(2)(3) MIN MAX 1.1V MIN 1.0V MAX MIN MAX Polarity = 0, Phase = 0, from SPI0_CLK falling 2.5P+17.5 2.5P+20 2.5P+27 Polarity = 0, Phase = 1, from SPI0_CLK rising 2.5P+17.5 2.5P+20 2.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 Table 6-72. General Timing Requirements for SPI1 Master Modes (1) 1.3V, 1.2V NO. 1.1V 1.0V MIN MAX MIN MAX MIN MAX 20 (2) 256P 30 (2) 256P 40 (2) 256P UNIT 1 tc(SPC)M Cycle Time, SPI1_CLK, All Master Modes 2 tw(SPCH)M Pulse Width High, SPI1_CLK, All Master Modes 0.5M-1 0.5M-1 0.5M-1 ns 3 tw(SPCL)M Pulse Width Low, SPI1_CLK, All Master Modes 0.5M-1 0.5M-1 0.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com Table 6-73. General Timing Requirements for SPI1 Slave Modes (1) 1.3V, 1.2V NO.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 Table 6-74. Additional (1) SPI1 Master Timings, 4-Pin Enable Option (2) (3) NO. 17 td(EN A_SPC)M 18 (1) (2) (3) (4) (5) 1.3V, 1.2V PARAMETER td(SPC_ENA)M Delay from slave assertion of SPI1_ENA active to first SPI1_CLK from master. (4) Max delay for slave to deassert SPI1_ENA after final SPI1_CLK edge to ensure master does not begin the next transfer. (5) MIN 1.1V MAX MIN MAX 1.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com Table 6-76. Additional (1) SPI1 Master Timings, 5-Pin Option (2) (3) NO. 18 1.3V, 1.2V PARAMETER td(SPC_ENA)M Max delay for slave to deassert SPI1_ENA after final SPI1_CLK edge to ensure master does not begin the next transfer. (4) MIN td(SPC_SCS)M td(SCSL_ENAL)M td(SCS_SPC)M 164 MAX 0.5M+P+6 Polarity = 0, Phase = 1, from SPI1_CLK falling P+5 P+5 P+6 Polarity = 1, Phase = 0, from SPI1_CLK rising 0.5M+P+5 0.5M+P+5 0.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 Table 6-76. Additional(1) SPI1 Master Timings, 5-Pin Option(2)(3) (continued) NO. 1.3V, 1.2V PARAMETER MIN MAX Polarity = 0, Phase = 0, to SPI1_CLK rising 23 td(ENA_SPC)M Delay from assertion of SPI1_ENA low to first SPI1_CLK edge. (10) 1.1V 1.0V MIN MAX 3P+5 Polarity = 0, Phase = 1, to SPI1_CLK rising MIN MAX 3P+5 0.5M+3P+5 UNIT 3P+6 0.5M+3P+5 0.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com Table 6-78. Additional(1) SPI1 Slave Timings, 4-Pin Chip Select Option(2)(3) (continued) NO. 1.3V, 1.2V PARAMETER MIN Polarity = 0, Phase = 0, from SPI1_CLK falling 26 td(SPC_SCSH)S Polarity = 0, Phase = 1, Required delay from final SPI1_CLK edge from SPI1_CLK falling before SPI1_SCS is deasserted. Polarity = 1, Phase = 0, from SPI1_CLK rising Polarity = 1, Phase = 1, from SPI1_CLK rising 1.1V MAX MIN 1.0V MAX MIN 0.5M+P+4 0.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 Table 6-79. Additional (1) SPI1 Slave Timings, 5-Pin Option (2) (3) NO. 25 26 27 1.3V, 1.2V PARAMETER td(SCSL_SPC)S td(SPC_SCSH)S tena(SCSL_SOMI) S MIN Required delay from SPI1_SCS asserted at slave to first SPI1_CLK edge at slave. Required delay from final SPI1_CLK edge before SPI1_SCS is deasserted. MIN P+1.5 Polarity = 0, Phase = 0, from SPI1_CLK falling 0.5M+P+4 0.5M+P+5 0.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 SLAVE MODE 4 PIN WITH ENABLE 24 SPIx_CLK SPIx_SOMI SO(0) SO(1) SO(n−1) SO(n) SPIx_SIMO SI(0) SPIx_ENA SI(1) SI(n−1) SI(n) SLAVE MODE 4 PIN WITH CHIP SELECT 26 25 SPIx_CLK 27 SPIx_SOMI 28 SO(n−1) SO(0) SO(1) SO(n) SPIx_SIMO SI(0) SPIx_SCS SI(1) SI(n−1) SI(n) SLAVE MODE 5 PIN 26 30 25 SPIx_CLK 27 SPIx_SOMI 28 SO(1) SO(0) SO(n−1) SO(n) SPIx_SIMO 29 SPIx_ENA DESEL(A) SI(0) SI(1) SI(n−1) SI(n) DESEL(A) SPIx_SCS A.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com 6.18 Inter-Integrated Circuit Serial Ports (I2C) 6.18.1 I2C Device-Specific Information Each I2C port supports: • Compatible with Philips® I2C Specification Revision 2.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 6.18.2 I2C Peripheral Registers Description(s) Table 6-80 is the list of the I2C registers. Table 6-80.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com 6.18.3 I2C Electrical Data/Timing 6.18.3.1 Inter-Integrated Circuit (I2C) Timing Table 6-81 and Table 6-82 assume testing over recommended operating conditions (see Figure 6-41 and Figure 6-42). Table 6-81. Timing Requirements for I2C Input 1.3V, 1.2V, 1.1V, 1.0V NO. Standard Mode MIN MAX Fast Mode MIN UNIT MAX 1 tc(SCL) Cycle time, I2Cx_SCL 10 2.5 μs 2 tsu(SCLH-SDAL) Setup time, I2Cx_SCL high before I2Cx_SDA low 4.7 0.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 11 9 I2Cx_SDA 6 8 14 4 13 5 10 I2Cx_SCL 1 12 3 2 7 3 Stop Start Repeated Start Stop Figure 6-41. I2C Receive Timings 26 24 I2Cx_SDA 21 23 19 28 20 25 I2Cx_SCL 16 27 18 17 22 18 Stop Start Repeated Start Stop Figure 6-42.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com 6.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 6.19.2 UART Electrical Data/Timing Table 6-84. Timing Requirements for UART Receive (1) (see Figure 6-43) 1.3V, 1.2V, 1.1V, 1.0V NO. MIN MAX UNIT 4 tw(URXDB) Pulse duration, receive data bit (RXDn) 0.96U 1.05U ns 5 tw(URXSB) Pulse duration, receive start bit 0.96U 1.05U ns (1) U = UART baud time = 1/programmed baud rate. Table 6-85.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com 6.20 Universal Serial Bus OTG Controller (USB0) [USB2.0 OTG] The USB2.0 peripheral supports the following features: • USB 2.0 peripheral at speeds high speed (HS: 480 Mb/s) and full speed (FS: 12 Mb/s) • USB 2.0 host at speeds HS, FS, and low speed (LS: 1.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 Table 6-86.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com Table 6-86.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 Table 6-86. Universal Serial Bus OTG (USB0) Registers (continued) BYTE ADDRESS ACRONYM 0x01E0 049C RXFUNCADDR REGISTER DESCRIPTION 0x01E0 049E RXHUBADDR Address of the hub that has to be accessed through the associated Receive Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub. 0x01E0 049F RXHUBPORT Port of the hub that has to be accessed through the associated Receive Endpoint.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com Table 6-86. Universal Serial Bus OTG (USB0) Registers (continued) BYTE ADDRESS 0x01E0 052B 0x01E0 052C 0x01E0 052D ACRONYM REGISTER DESCRIPTION HOST_TXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host Transmit endpoint. HOST_RXTYPE Sets the operating speed, transaction protocol and peripheral endpoint number for the host Receive endpoint.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 Table 6-86.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com 6.20.1 USB0 [USB2.0] Electrical Data/Timing The USB PHY PLL can support input clock of the following frequencies: 12.0 MHz, 13.0 MHz, 19.2 MHz, 20.0 MHz, 24.0 MHz, 26.0 MHz, 38.4 MHz, 40.0 MHz or 48.0 MHz. USB_REFCLKIN jitter tolerance is 50 ppm maximum. Table 6-87. Switching Characteristics Over Recommended Operating Conditions for USB0 [USB2.0] (see Figure 6-44) 1.3V, 1.2V, 1.1V, 1.0V NO. LOW SPEED 1.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 6.21 Universal Serial Bus Host Controller (USB1) [USB1.1 OHCI] All the USB interfaces for this device are compliant with Universal Serial Bus Specifications, Revision 1.1. Table 6-88 is the list of USB Host Controller registers. Table 6-88.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com 6.22 Ethernet Media Access Controller (EMAC) The Ethernet Media Access Controller (EMAC) provides an efficient interface between device and the network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QOS) support. The EMAC controls the flow of packet data from the device to the PHY.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 Table 6-90.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com Table 6-90.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 Table 6-91.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com Table 6-93. EMAC Control Module RAM BYTE ADDRESS DESCRIPTION 0x01E2 0000 - 0x01E2 1FFF EMAC Local Buffer Descriptor Memory 6.22.2 EMAC Electrical Data/Timing Table 6-94. Timing Requirements for MII_RXCLK (see Figure 6-45) 1.3V, 1.2V, 1.1V NO. 10 Mbps MIN MAX 1.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 Table 6-96. Timing Requirements for EMAC MII Receive 10/100 Mbit/s (1) (see Figure 6-47) 1.3V, 1.2V, 1.1V, 1.0V NO. MIN UNIT MAX 1 tsu(MRXD-MII_RXCLKH) Setup time, receive selected signals valid before MII_RXCLK high 8 ns 2 th(MII_RXCLKH-MRXD) Hold time, receive selected signals valid after MII_RXCLK high 8 ns (1) Receive selected signals include: MII_RXD[3]-MII_RXD[0], MII_RXDV, and MII_RXER.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com Table 6-98. Timing Requirements for EMAC RMII 1.3V, 1.2V, 1.1V (1) NO.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 6.23 Management Data Input/Output (MDIO) The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system. The Management Data Input/Output (MDIO) module implements the 802.3 serial management interface to interrogate and control Ethernet PHY(s) using a shared two-wire bus.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com 6.23.2 Management Data Input/Output (MDIO) Electrical Data/Timing Table 6-101. Timing Requirements for MDIO Input (see Figure 6-50 and Figure 6-51) 1.3V, 1.2V, 1.1V NO. MIN MAX 1.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 6.24 LCD Controller (LCDC) The LCD controller consists of two independent controllers, the Raster Controller and the LCD Interface Display Driver (LIDD) controller. Each controller operates independently from the other and only one of them is active at any given time. • The Raster Controller handles the synchronous LCD interface. It provides timing and data for constant graphics refresh to a passive display.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com 6.24.1 LCD Interface Display Driver (LIDD Mode) Table 6-104. Timing Requirements for LCD LIDD Mode 1.3V, 1.2V, 1.1V NO. MIN MAX 1.0V MIN UNIT MAX 16 tsu(LCD_D) Setup time, LCD_D[15:0] valid before LCD_MCLK high 7 8 ns 17 th(LCD_D) Hold time, LCD_D[15:0] valid after LCD_MCLK high 0 0 ns Table 6-105. Switching Characteristics Over Recommended Operating Conditions for LCD LIDD Mode NO. 1.3V, 1.2V, 1.1V PARAMETER 1.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 W_HOLD (1–15) R_SU (0–31) 1 2 R_STROBE R_HOLD (1–63) (1–5) CS_DELAY W_SU W_STROBE (0–31) CS_DELAY (1–63) Not Used 3 LCD_MCLK 14 16 17 15 4 LCD_D[7:0] 5 Data[7:0] Write Instruction Read Data LCD_PCLK Not Used 8 9 RS LCD_VSYNC 10 11 LCD_HSYNC R/W 12 13 12 13 LCD_AC_ENB_CS E0 E1 Figure 6-53.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com W_HOLD (1−15) W_HOLD (1−15) 1 2 W_SU W_STROBE (0−31) (1−63) CS_DELAY W_SU W_STROBE (0−31) (1−63) CS_DELAY 3 Clock LCD_MCLK 4 LCD_D[15:0] LCD_AC_ENB_CS (async mode) 5 5 4 Write Address Write Data 7 6 Data[15:0] 6 7 CS0 CS1 9 8 A0 LCD_VSYNC 10 11 11 10 R/W LCD_HSYNC 12 13 12 13 E LCD_PCLK Figure 6-54.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 W_HOLD (1−15) 1 2 W_SU W_STROBE (0−31) (1−63) R_SU (0−31) CS_DELAY R_STROBE R_HOLD (1−63 CS_DELAY (1−15) 3 Clock LCD_MCLK 4 LCD_D[15:0] 5 14 16 17 15 Write Address Data[15:0] 6 7 Read Data 6 7 LCD_AC_ENB_CS (async mode) CS0 CS1 9 8 LCD_VSYNC A0 11 10 LCD_HSYNC R/W 12 13 12 13 LCD_PCLK E Figure 6-55.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com R_SU (0−31) R_SU (0−31) R_STROBE R_HOLD CS_DELAY R_STROBE R_HOLD CS_DELAY 1 2 (1−63) 3 (1−15) (1−63) (1−15) Clock LCD_MCLK 14 16 17 15 14 17 16 15 LCD_D[15:0] Data[15:0] Read Data 6 LCD_AC_ENB_CS (async mode) 7 Read Status 6 7 CS0 CS1 8 9 LCD_VSYNC A0 R/W LCD_HSYNC 12 13 12 13 E LCD_PCLK Figure 6-56.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 W_HOLD (1−15) W_HOLD (1−15) 1 2 W_SU W_STROBE (0−31) 3 (1−63) CS_DELAY W_SU W_STROBE (0−31) (1−63) CS_DELAY Clock LCD_MCLK 4 LCD_D[15:0] LCD_AC_ENB_CS (async mode) 5 4 Write Address 5 DATA[15:0] Write Data 7 6 6 7 CS0 CS1 8 9 LCD_VSYNC A0 10 11 10 11 LCD_HSYNC WR RD LCD_PCLK Figure 6-57.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com W_HOLD (1−15) W_SU W_STROBE R_SU (0−31) CS_DELAY R_STROBE R_HOLD CS_DELAY 1 2 3 (0−31) (1−63) (1−63) (1−15) 16 17 Clock LCD_MCLK 4 LCD_D[15:0] 5 14 15 Data[15:0] Write Address 6 7 LCD_AC_ENB_CS (async mode) 6 Read Data 7 CS0 CS1 9 8 LCD_VSYNC A0 10 11 WR LCD_HSYNC 12 13 RD LCD_PCLK Figure 6-58.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 R_SU (0−31) R_SU (0−31) R_STROBE 1 2 (1−63) R_HOLD CS_DELAY R_STROBE R_HOLD (1−15) (1−63) CS_DELAY (1−15) 3 Clock LCD_MCLK 14 16 17 15 14 16 17 15 Data[15:0] LCD_D[15:0] Read Data Read Status 7 6 6 7 LCD_AC_ENB_CS CS0 CS1 8 9 A0 LCD_VSYNC WR LCD_HSYNC 12 13 12 13 RD LCD_PCLK Figure 6-59.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com 6.24.2 LCD Raster Mode Table 6-106. Switching Characteristics Over Recommended Operating Conditions for LCD Raster Mode See Figure 6-60 through Figure 6-64 NO. PARAMETER 1.3V, 1.2V, 1.1V MIN MAX 1.0V MIN UNIT MAX 1 tc(PIXEL_CLK) Cycle time, pixel clock 26.66 33.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 Data Pixels (From 1 to P) 1, 1 2, 1 1, 2 2, 2 P−2, 1 3, 1 P−1, 1 P, 1 P−1, 2 P, 2 P, 3 Data Lines (From 1 to L) 1, 3 LCD P, L−2 1, L−2 1, L−1 2, L−1 1, L 2, L P−1, L−1 P−2, L 3, L P−1, L P, L−1 P, L Figure 6-60.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 Figure 6-62.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com 6 LCD_AC_ENB_CS 8 LCD_VSYNC 10 11 LCD_HSYNC 1 2 3 LCD_PCLK (passive mode) 5 4 LCD_D[7:0] (passive mode) 1, L 2, L P, L 1, 1 2, 1 P, 1 1 2 3 LCD_PCLK (active mode) 4 LCD_D[15:0] (active mode) VBP = 0 VFP = 0 VSW = 1 1, L 2, L PPL 16 × (1 to 1024) 5 P, L HFP (1 to 256 HSW (1 to 64) Line L HBP (1 to 256) PPL 16 ×(1 to 1024) Line 1 (Passive Only) Figure 6-63.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 7 LCD_AC_ENB_CS 9 LCD_VSYNC 10 11 LCD_HSYNC 1 3 4 LCD_PCLK (passive mode) 5 4 LCD_D[7:0] (passive mode) 1, 1 2, 1 P, 1 1, 2 2, 2 P, 2 1 2 3 LCD_PCLK (active mode) 4 LCD_D[15:0] (active mode) VBP = 0 VFP = 0 VSW = 1 5 1, 1 PPL 16 × (1 to 1024) HFP (1 to 256 HSW (1 to 64) HBP (1 to 256) Line 1 for passive 2, 1 P, 1 PPL 16 ×(1 to 1024) Line 1 for active Line 2 for passive Figure 6-64.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com 6.25 Host-Port Interface (UHPI) 6.25.1 HPI Device-Specific Information The device includes a user-configurable 16-bit Host-port interface (HPI16). The host port interface (UHPI) provides a parallel port interface through which an external host processor can directly access the processor's resources (configuration and program/data memories).
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 6.25.3 HPI Electrical Data/Timing Table 6-108. Timing Requirements for Host-Port Interface [1.3V, 1.2V, 1.1V] (1) (2) 1.3V, 1.2V, 1.1V, 1.0V NO.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com Table 6-109. Switching Characteristics Over Recommended Operating Conditions for Host-Port Interface [1.3V, 1.2V, 1.1V] (1) (2) (3) NO. 1.3V, 1.2V PARAMETER MIN MAX 1.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 Table 6-110. Switching Characteristics Over Recommended Operating Conditions for Host-Port Interface [1.0V] (1) (2) (3) NO. PARAMETER 1.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com UHPI_HCS UHPI_HAS(D) 2 2 1 1 UHPI_HCNTL[1:0] 2 1 2 1 UHPI_HR/W 2 2 1 1 UHPI_HHWIL 4 3 3 UHPI_HSTROBE(A)(C) 15 15 14 14 6 8 6 8 UHPI_HD[15:0] (output) 5 13 7 1st Half-Word 2nd Half-Word UHPI_HRDY(B) A. UHPI_HSTROBE refers to the following logical operation on UHPI_HCS, UHPI_HDS1, and UHPI_HDS2: [NOT(HDS1 XOR HDS2)] OR UHPI_HCS. B.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 UHPI_HAS(A) 17 10 17 9 10 9 UHPI_HCNTL[1:0] 10 10 9 9 UHPI_HR/W 10 10 9 9 UHPI_HHWIL 4 3 UHPI_HSTROBE(B) 16 16 UHPI_HCS 14 UHPI_HD[15:0] 6 (output) 5a 8 1st half-word 14 15 7 8 2nd half-word UHPI_HRDY A. B. For correct operation, strobe the UHPI_HAS signal only once per UHPI_HSTROBE active cycle.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com UHPI_HCS UHPI_HAS(D) 1 1 2 2 UHPI_HCNTL[1:0] 1 1 2 2 UHPI_HR/W 1 1 2 2 UHPI_HHWIL 3 3 4 UHPI_HSTROBE(A)(C) 11 UHPI_HD[15:0] (input) 11 12 12 1st Half-Word 5 13 2nd Half-Word 18 13 18 5 UHPI_HRDY(B) A. UHPI_HSTROBE refers to the following logical operation on UHPI_HCS, UHPI_HDS1, and UHPI_HDS2: [NOT(HDS1 XOR HDS2)] OR UHPI_HCS. B.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 17 UHPI_HAS† 17 10 10 9 9 UHPI_HCNTL[1:0] 10 10 9 9 UHPI_HR/W 10 10 9 9 UHPI_HHWIL 3 4 UHPI_HSTROBE‡ 16 16 UHPI_HCS 11 12 UHPI_HD[15:0] (input) 1st half-word 5a 11 12 2nd half-word 13 UHPI_HRDY A. B. For correct operation, strobe the UHPI_HAS signal only once per UHPI_HSTROBE active cycle.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com 6.26 Universal Parallel Port (uPP) The Universal Parallel Port (uPP) peripheral is a multichannel, high-speed parallel interface with dedicated data lines and minimal control signals. It is designed to interface cleanly with high-speed analog-to-digital converters (ADCs) or digital-to-analog converters (DACs) with up to 16-bit data width (per channel).
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 6.26.1 uPP Register Descriptions Table 6-111.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com 6.26.2 uPP Electrical Data/Timing Table 6-112. Timing Requirements for uPP (see Figure 6-69, Figure 6-70, Figure 6-71, Figure 6-72) 1.3V, 1.2V NO. MIN MAX 1.1V MIN 1.0V MAX MIN SDR mode 13.33 20 26.66 DDR mode 26.66 40 53.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 1 2 3 CHx_CLK 4 5 CHx_START 6 7 CHx_ENABLE CHx_WAIT 8 9 CHx_DATA[n:0] CHx_XDATA[n:0] Data1 Data2 Data3 Data4 Data5 Data7 Data6 Data8 Data9 Figure 6-69. uPP Single Data Rate (SDR) Receive Timing 1 2 3 CHx_CLK 4 5 CHx_START 6 7 CHx_ENABLE CHx_WAIT 8 CHx_DATA[n:0] CHx_XDATA[n:0] I1 Q1 I2 Q2 I3 Q3 10 9 I4 Q4 I5 Q5 I6 Q6 I7 11 Q7 I8 Q8 I9 Q9 Figure 6-70.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com 12 13 14 CHx_CLK 15 CHx_START 16 CHx_ENABLE 19 20 CHx_WAIT 17 CHx_DATA[n:0] CHx_XDATA[n:0] Data1 Data2 Data3 Data4 Data5 Data6 Data7 Data8 Data9 Figure 6-71. uPP Single Data Rate (SDR) Transmit Timing 12 13 14 CHx_CLK 15 CHx_START 16 CHx_ENABLE 19 20 CHx_WAIT 17 CHx_DATA[n:0] CHx_XDATA[n:0] I1 Q1 18 I2 Q2 I3 Q3 I4 Q4 I5 Q5 I6 Q6 I7 Q7 I8 Q8 I9 Q9 Figure 6-72.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 6.27 Video Port Interface (VPIF) The Video Port Interface (VPIF) allows the capture and display of digital video streams. Features include: • Up to 2 Video Capture Channels (Channel 0 and Channel 1) – Two 8-bit Standard-Definition (SD) Video with embedded timing codes (BT.656) – Single 16-bit High-Definition (HD) Video with embedded timing codes (BT.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com Table 6-114.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 Table 6-114.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com 6.27.2 VPIF Electrical Data/Timing Table 6-115. Timing Requirements for VPIF VP_CLKINx Inputs (1) (see Figure 6-73) 1.3V, 1.2V NO. MIN 1.1V MAX MIN 1.0V MAX MIN MAX UNIT Cycle time, VP_CLKIN0 13.3 20 37 ns Cycle time, VP_CLKIN1/2/3 13.3 20 37 ns tw(VKIH) Pulse duration, VP_CLKINx high 0.4C 0.4C 0.4C ns 3 tw(VKIL) Pulse duration, VP_CLKINx low 0.4C 4 tt(VKI) Transition time, VP_CLKINx 1 tc(VKI) 2 (1) 0.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 Table 6-117. Switching Characteristics Over Recommended Operating Conditions for Video Data Shown With Respect to VP_CLKOUT2/3 (1) (see Figure 6-75) NO. 1.3V, 1.2V PARAMETER MIN 1.1V MAX MIN 1.0V MAX MIN MAX UNIT 1 tc(VKO) Cycle time, VP_CLKOUT2/3 13.3 20 37 ns 2 tw(VKOH) Pulse duration, VP_CLKOUT2/3 high 0.4C 0.4C 0.4C ns 3 tw(VKOL) Pulse duration, VP_CLKOUT2/3 low 0.4C 0.4C 0.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com 6.28 Enhanced Capture (eCAP) Peripheral The device contains up to three enhanced capture (eCAP) modules. Figure 6-76 shows a functional block diagram of a module. Uses for ECAP include: • Speed measurements of rotating machinery (e.g.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 SYNC www.ti.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com Table 6-118 is the list of the ECAP registers. Table 6-118.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 6.29 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) The device contains two enhanced PWM Modules (eHRPWM). Figure 6-77 shows a block diagram of multiple eHRPWM modules. Figure 4-4 shows the signal interconnections with the eHRPWM.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com 6.29.2 Enhanced Pulse Width Modulator (eHRPWM) Timing PWM refers to PWM outputs on eHRPWM1-6. Table 6-121 shows the PWM timing requirements and Table 6-122, switching characteristics. Table 6-121. Timing Requirements for eHRPWM tw(SYNCIN) Sync input pulse width TEST CONDITIONS 1.3V, 1.2V, 1.1V, 1.0V Asynchronous 2tc(SCO) cycles Synchronous 2tc(SCO) cycles MIN MAX UNIT Table 6-122.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 6.29.3 Trip-Zone Input Timing tw(TZ) TZ td(TZ-PWM)HZ PWM(A) A. PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM recovery software. Figure 6-79. PWM Hi-Z Characteristics Table 6-123. Trip-Zone input Timing Requirements TEST CONDITIONS 1.3V, 1.2V, 1.1V, 1.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com 6.30 Timers The timers support the following features: • Configurable as single 64-bit timer or two 32-bit timers • Period timeouts generate interrupts, DMA events or external pin events • 8 32-bit compare registers • Compare matches generate interrupt events • Capture capability • 64-bit Watchdog capability (Timer64P1 only) Table 6-124 lists the timer registers. Table 6-124.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 6.30.1 Timer Electrical Data/Timing Table 6-125. Timing Requirements for Timer Input (1) (2) (see Figure 6-80) 1.3V, 1.2V, 1.1V, 1.0V NO. MIN 1 tc(TM64Px_IN12) Cycle time, TM64Px_IN12 2 tw(TINPH) Pulse duration, TM64Px_IN12 high 0.45C 3 tw(TINPL) Pulse duration, TM64Px_IN12 low 0.45C 4 tt(TM64Px_IN12) Transition time, TM64Px_IN12 (1) (2) (3) MAX UNIT 4P ns 0.55C ns 0.55C ns 0.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com 6.31 Real Time Clock (RTC) The RTC provides a time reference to an application running on the device. The current date and time is tracked in a set of counter registers that update once per second. The time can be represented in 12-hour or 24-hour mode. The calendar and time registers are buffered during reads and writes so that updates do not interfere with the accuracy of the time and date.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 6.31.1 Clock Source The clock reference for the RTC is an external 32.768-kHz crystal or an external clock source of the same frequency. The RTC also has a separate power supply that is isolated from the rest of the system. When the CPU and other peripherals are without power, the RTC can remain powered to preserve the current time and calendar information.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com 6.31.2 Real-Time Clock Register Descriptions Table 6-127.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 6.32 General-Purpose Input/Output (GPIO) The GPIO peripheral provides general-purpose pins that can be configured as either inputs or outputs. When configured as an output, a write to an internal register can control the state driven on the output pin. When configured as an input, the state of the input is detectable by reading the state of an internal register.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com 6.32.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 6.32.2 www.ti.com GPIO Peripheral Input/Output Electrical Data/Timing Table 6-128. Timing Requirements for GPIO Inputs (1) (see Figure 6-84) 1.3V, 1.2V, 1.1V, 1.0V NO. MIN MAX UNIT 1 tw(GPIH) Pulse duration, GPn[m] as input high 2C (1) (2) ns 2 tw(GPIL) Pulse duration, GPn[m] as input low 2C (1) (2) ns (1) The pulse width given is sufficient to generate a CPU interrupt or an EDMA event.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 6.33 Programmable Real-Time Unit Subsystem (PRUSS) The Programmable Real-Time Unit Subsystem (PRUSS) consists of • Two Programmable Real-Time Units (PRU0 and PRU1) and their associated memories • An Interrupt Controller (INTC) for handling system interrupt events. The INTC also supports posting events back to the device level host CPU.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com Table 6-133.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 Table 6-135.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com 6.34 Emulation Logic This section describes the steps to use a third party debugger on the ARM926EJ-S within the device. The debug capabilities and features for ARM are as shown below.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 Table 6-136. ARM Debug Features Category Hardware Feature Availability Software breakpoint Unlimited Up to 14 HWBPs, including: 2 precise (1) HWBP inside ARM core which are shared with watch points. Basic Debug Hardware breakpoint 8 imprecise (1) HWBPs from ETM’s address comparators, which are shared with trace function, and can be used as watch points. 4 imprecise (1) HWBPs from ICECrusher.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com Table 6-137. JTAG Port Description (continued) PIN TYPE NAME EMU0 I/O Emulation 0 Channel 0 trigger + HSRTDX DESCRIPTION EMU1 I/O Emulation 1 Channel 1 trigger + HSRTDX 6.34.2 Scan Chain Configuration Parameters Table 6-138 shows the TAP configuration details required to configure the router/emulator for this device. Table 6-138.
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AM1808 www.ti.com • • • • • • • • SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 Function : Update the JTAG preamble and post-amble counts. – Parameter : The IR pre-amble count is '0'. – Parameter : The IR post-amble count is '0'. – Parameter : The DR pre-amble count is '0'. – Parameter : The DR post-amble count is '0'. – Parameter : The IR main count is '6'. – Parameter : The DR main count is '1'. Function : Do a send-only JTAG IR/DR scan.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 • www.ti.com Function : Update the JTAG preamble and post-amble counts. – Parameter : The IR pre-amble count is '0'. – Parameter : The IR post-amble count is '6'. – Parameter : The DR pre-amble count is '0'. – Parameter : The DR post-amble count is '1'. – Parameter : The IR main count is '4'. – Parameter : The DR main count is '1'. The initial scan chain contains only the TAP router module.
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AM1808 www.ti.com • • • • SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 Function : Do a send-only JTAG IR/DR scan. – Parameter : The route to JTAG shift state is 'shortest transition'. – Parameter : The JTAG shift state is 'shift-dr'. – Parameter : The JTAG destination state is 'pause-dr'. – Parameter : The bit length of the command is '32'. – Parameter : The send data value is '0xa3302108'. – Parameter : The actual receive data is 'discarded'. Function : Do a send-only all-ones JTAG IR/DR scan.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com 6.34.4 IEEE 1149.1 JTAG The JTAG (1) interface is used for BSDL testing and emulation of the device. The device requires that both TRST and RESET be asserted upon power up to be properly initialized. While RESET initializes the device, TRST initializes the device's emulation logic. Both resets are required for proper operation.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 Table 6-140. JTAG ID Register Selection Bit Descriptions BIT NAME 31:28 VARIANT DESCRIPTION Variant (4-Bit) value 27:12 PART NUMBER Part Number (16-Bit) value 11-1 MANUFACTURER Manufacturer (11-Bit) value 0 LSB 6.34.4.2 LSB. This bit is read as a "1". JTAG Test-Port Electrical Data/Timing Table 6-141. Timing Requirements for JTAG Test Port (see Figure 6-89) 1.3V, 1.2V No. MIN MAX 1.1V MIN 1.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 www.ti.com 7 Device and Documentation Support 7.1 7.1.1 Device Support Development Support TI offers an extensive line of development tools for the device platform, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules.
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AM1808 www.ti.com SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 X AM1808 ZKB ( ) 3 DEVICE SPEED RANGE 3 = 300 MHz (for revision A) 3 = 375 MHz (for revision B) 4 = 456 MHz PREFIX X = Experimental Device P = Prototype Device Blank = Production Device TEMPERATURE RANGE (JUNCTION) Blank = 0°C to 90°C (Commercial Grade) D = -40°C to 90°C (Industrial Grade) A = -40°C to 105°C (Extended Grade) DEVICE (B) SILICON REVISION A = Silicon Revision 1.1 B = Silicon Revision 2.0 or 2.1 E = Silicon Revision 2.
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AM1808 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 7.5 www.ti.com Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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AM1808 www.ti.com 8.2 SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014 Thermal Data for ZWT Package The following table(s) show the thermal resistance characteristics for the PBGA–ZWT mechanical package. Table 8-2. Thermal Resistance Characteristics (PBGA Package) [ZWT] °C/W (1) NO. 1 RΘJC Junction-to-case 7.3 N/A 2 RΘJB Junction-to-board 12.4 N /A 3 RΘJA Junction-to-free air 23.7 0.00 4 21.0 0.50 5 20.1 1.00 6 Junction-to-moving air 19.3 2.00 18.4 4.00 8 0.2 0.00 9 0.3 0.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 12-Feb-2014 TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.