Datasheet

Table Of Contents
TMS320DM6467T
www.ti.com
SPRS605C JULY 2009REVISED JUNE 2012
4.3.3 Clock and Oscillator Control
The Clock and Oscillator Control (CLKCTL) register allows the user to disable the OSC pwrdwn and pwr
disable
31 26 25 24 23 20 19 16
RESERVED OSCPWRDN OSCDIS RESERVED CLKOUT
R-0000 00 R/W-0 R/W-1 R-0000 R/W-1000
15 12 11 8 7 4 3 0
RESERVED AUD_CLK1 RESERVED AUD_CLK0
R-0000 R/W-0000 R-0000 R/W-0000
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 4-5. CLKCTL Register [0x01C4 005C]
Table 4-7. CLKCTL Register Bit Descriptions
BIT NAME DESCRIPTION
31:26 RESERVED Reserved. Read returns "0".
25 OSCPWRDN Auxiliary Oscillator Powerdown.
This bit controls the internal bias resistor conection.
0 = Internal bias resistor connected (normal operation)
1 = Internal bias resistor disconnected (external bias resistor required or clock input used)
24 OSCDIS Auxiliary Oscillator Disable.
This bit disables the oscillator.
0 = Oscillator enabled (normal operation).
1 = Oscillator disabled (clock input used or no Auxiliary clock required).
23:20 RESERVED Reserved. Read returns "0".
19:16 CLKOUT CLKOUT0 Source
(1)
This field selects the clock source for the CLKOUT0 output.
0000 = Disabled
0001 = PLL1 AUXCLK
0010 = Reserved
0011 = SYSCLK3
0100 = SYSCLK4
0101 = SYSCLK5
0110 = SYSCLK6
0111 = Reserved
1000 = SYSCLK8
1001 = SYSCLK9
1010 = AUX_MXI
1011 = Reserved
1100 = Reserved
1101 = Reserved
1110 = Reserved
1111 = Reserved
15:12 RESERVED Reserved. Read returns "0".
(1) The maximum frequency allowed for the CLKOUT0 pin is 148.5 MHz. Do not configure the CLKOUT bits to any SYSCLKx that is greater
than 148.5 MHz. For more details on the CLKOUT0 timings, see Table 7-14, Switching Characteristics Over Recommended Operating
Conditions for CLKOUT0.
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