Datasheet

TMS320DM6467T
SPRS605C –JULY 2009–REVISED JUNE 2012 www.ti.com
4.3.2.3 Video and TSIF Clock Disable
The Video Source Clock Disable (VSCLKDIS) register allows the user to disable the selected Video
(VPIF), TSIF, and CRGEN module input clocks.
Note: To ensure glitch-free operation, the clock should be disabled before changing the clock source
frequency or muxing via the VIDCLKCTL and TSIFCTL.
31 16
RESERVED
R-0000 0000 0000 0000
15 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED VID3 VID2 VID1 VID0 TSIFCNT1 TSIFCNT0 TSIFTX1 TSIFTX0 TSIFRX1 TSIFRX0 CRG1 CRG0
R-0000 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 4-4. VSCLKDIS Register [0x01C4 006C]
Table 4-6. VSCLKDIS Register Bit Descriptions
BIT NAME DESCRIPTION
31:12 RESERVED Reserved. Read returns "0".
VPIF Channel 3 Clock Disable.
11 VID3 0 = Clock enabled.
1 = Clock disabled.
VPIF Channel 2 Clock Disable.
10 VID2 0 = Clock enabled.
1 = Clock disabled.
VPIF Channel 1 Clock Disable.
9 VID1 0 = Clock enabled.
1 = Clock disabled.
VPIF Channel 0 Clock Disable.
8 VID0 0 = Clock enabled.
1 = Clock disabled.
TSIF1 Counter Clock Disable.
7 TSIFCNT1 0 = Clock enabled.
1 = Clock disabled.
TSIF0 Counter Clock Disable.
6 TSIFCNT0 0 = Clock enabled.
1 = Clock disabled.
TSIF1 Transmit Clock Disable.
5 TSIFTX1 0 = Clock enabled.
1 = Clock disabled.
TSIF0 Transmit Clock Disable.
4 TSIFTX0 0 = Clock enabled.
1 = Clock disabled.
TSIF1 Receive Clock Disable.
3 TSIFRX1 0 = Clock enabled.
1 = Clock disabled.
TSIF0 Receive Clock Disable.
2 TSIFRX0 0 = Clock enabled.
1 = Clock disabled.
CRGEN1 Clock Disable.
1 CRG1 0 = Clock enabled.
1 = Clock disabled.
CRGEN0 Clock Disable.
0 CRG0 0 = Clock enabled.
1 = Clock disabled.
90 Device Configurations Copyright © 2009–2012, Texas Instruments Incorporated
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