Datasheet
Table Of Contents
- 1 Digital Media System-on-Chip (DMSoC)
- Table of Contents
- 2 Revision History
- 3 Device Overview
- 3.1 Device Characteristics
- 3.2 Device Compatibility
- 3.3 ARM Subsystem
- 3.3.1 ARM926EJ-S RISC CPU
- 3.3.2 CP15
- 3.3.3 MMU
- 3.3.4 Caches and Write Buffer
- 3.3.5 Tightly Coupled Memory (TCM)
- 3.3.6 Advanced High-Performance Bus (AHB)
- 3.3.7 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)
- 3.3.8 ARM Memory Mapping
- 3.3.9 Peripherals
- 3.3.10 PLL Controller (PLLC)
- 3.3.11 Power and Sleep Controller (PSC)
- 3.3.12 ARM Interrupt Controller (AINTC)
- 3.3.13 System Module
- 3.3.14 Power Management
- 3.4 DSP Subsystem
- 3.5 Memory Map Summary
- 3.6 Pin Assignments
- 3.7 Terminal Functions
- 3.8 Device Support
- 3.9 Documentation Support
- 3.10 Community Resources
- 4 Device Configurations
- 4.1 System Module Registers
- 4.2 Power Considerations
- 4.3 Clock Considerations
- 4.4 Boot Sequence
- 4.5 Configurations At Reset
- 4.6 Configurations After Reset
- 4.7 Multiplexed Pin Configurations
- 4.7.1 Pin Muxing Selection At Reset
- 4.7.2 Pin Muxing Selection After Reset
- 4.7.3 Pin Multiplexing Details
- 4.7.3.1 PCI, HPI, EMIFA, and ATA Pin Muxing
- 4.7.3.2 PWM Signal Muxing
- 4.7.3.3 TSIF0 Input Signal Muxing (Serial/Parallel)
- 4.7.3.4 TSIF0 Output Signal Muxing (Serial/Parallel)
- 4.7.3.5 TSIF1 Input Signal Muxing (Serial Only)
- 4.7.3.6 TSIF1 Output Signal Muxing (Serial Only)
- 4.7.3.7 CRGEN Signal Muxing
- 4.7.3.8 UART0 Pin Muxing
- 4.7.3.9 UART1 Pin Muxing
- 4.7.3.10 UART2 Pin Muxing
- 4.7.3.11 ARM/DSP Communications Interrupts
- 4.7.3.12 Emulation Control
- 4.8 Debugging Considerations
- 5 System Interconnect
- 6 Device Operating Conditions
- 7 Peripheral Information and Electrical Specifications
- 7.1 Parameter Information
- 7.2 Recommended Clock and Control Signal Transition Behavior
- 7.3 Power Supplies
- 7.4 External Clock Input From DEV_MXI/DEV_CLKIN and AUX_MXI/AUX_CLKIN Pins
- 7.5 Clock PLLs
- 7.6 Enhanced Direct Memory Access (EDMA3) Controller
- 7.7 Reset
- 7.8 Interrupts
- 7.9 External Memory Interface (EMIF)
- 7.10 DDR2 Memory Controller
- 7.10.1 DDR2 Memory Controller Electrical Data/Timing
- 7.10.2 DDR2 Interface
- 7.10.2.1 DDR2 Interface Schematic
- 7.10.2.2 Compatible JEDEC DDR2 Devices
- 7.10.2.3 PCB Stackup
- 7.10.2.4 Placement
- 7.10.2.5 DDR2 Keep Out Region
- 7.10.2.6 Bulk Bypass Capacitors
- 7.10.2.7 High-Speed Bypass Capacitors
- 7.10.2.8 Net Classes
- 7.10.2.9 DDR2 Signal Termination
- 7.10.2.10 VREF Routing
- 7.10.2.11 DDR2 CK and ADDR_CTRL Routing
- 7.11 Video Port Interface (VPIF)
- 7.12 Transport Stream Interface (TSIF)
- 7.13 Clock Recovery Generator (CRGEN)
- 7.14 Video Data Conversion Engine (VDCE)
- 7.15 Peripheral Component Interconnect (PCI)
- 7.16 Ethernet MAC (EMAC)
- 7.17 Management Data Input/Output (MDIO)
- 7.18 Host-Port Interface (HPI) Peripheral
- 7.19 USB 2.0 [see Note]
- 7.20 ATA Controller
- 7.21 VLYNQ
- 7.22 Multichannel Audio Serial Port (McASP0/1) Peripherals
- 7.23 Serial Peripheral Interface (SPI)
- 7.24 Universal Asynchronouse Receiver/Transmitter (UART)
- 7.25 Inter-Integrated Circuit (I2C)
- 7.26 Pulse Width Modulator (PWM)
- 7.27 Timers
- 7.28 General-Purpose Input/Output (GPIO)
- 7.29 IEEE 1149.1 JTAG
- 8 Mechanical Packaging and Orderable Information
TMS320DM6467T
SPRS605C –JULY 2009–REVISED JUNE 2012
www.ti.com
Table 4-2. VDD3P3V_PWDN Register Bit Descriptions
BIT NAME DESCRIPTION
31:29 RESERVED Reserved. Read returns "0".
USB_DRVVBUS Powerdown Control.
0 = I/O cells powered up.
28 USBV
1 = I/O cells powered down.
This bit controls the USB_DRVVBUS/GP[22] pin.
CLKOUT0 Powerdown Control.
27 CLKOUT
This bit controls the CLKOUT0 pin.
26 RSV Reserved. Read returns "0".
SPI Powerdown Control.
25 SPI This bit controls the six SPI interface pins: SPI_CLK, SPI_EN, SPI_CS0, SPI_CS1, SPI_SOMI, and
SPI_SIMO.
VLYNQ Powerdown Control.
24 VLYNQ This bit controls the ten VLYNQ interface pins: VLYNQ_CLOCK, VLYNQ_SCRUN,
VLYNQ_TXD[3:0], and VLYNQ_RXD[3:0].
23:22 RESERVED Reserved. Read returns "0".
GMII Powerdown Control.
21 GMII This bit controls the ten pins used by GMII (Gigabit) only: RFTCLK, GMTCLK, MTXD[7:4], and
MRXD[7:4].
MII Powerdown Control.
20 MII This bit controls the 17 pins used by (G)MII (10/100/1000) and MDIO interfaces: MTCLK,
MTXD[3:0], MTXEN, MCOL, MCRS, MRCLK, MRXD[3:0], MRXDV, MRXER, MDCLK, and MDIO.
McASP1 Powerdown Control.
19 MCASP1
This bit controls the three McASP1 pins: ACLKX1, AHCLKX1, and AXR1[0].
McASP0 Powerdown Control.
18 MCASP0 This bit controls the 12 McASP0 pins: ACLKR0, AHCLKR0, AFSR0, ACLKX0, AHCLKX0, AFSX0,
AXR0[3:0], AMUTE0, and AMUTEIN0.
PCI/HPI/EMIFA/ATA Powerdown Control.
This bit controls the 28 pins used by the ATA or PCI`, HPI, or EMIFA. These pins include:
PCI_RST/DA2/GP[13]/EM_A[22], PCI_IDSEL/HDDIR/EM_R/W,
PCI_REQ/DMARQ/GP[11]/EM_CS5, PCI_GNT/DMACK/GP[12]/EM_CS4,
17 PCIHPI1 PCI_CBE1/ATA_CS1/GP[32]/EM_A[19], PCI_CBE0/ATA_CS0/GP[33]/EM_A[18],
DIOW/GP[20]/EM_WAIT4/(RDY4/BSY4), IORDY/GP[21]/EM_WAIT3/(RDY3/BSY3),
DIOR/GP[19]/EM_WAIT5/(RDY5/BSY5), DA1/GP[16]/EM_A[21], DA0/GP[17]/EM_A[20],
INTRQ/GP[18]/RSV , PCI_AD[31:16]/DD[15:0]/HD[31:16]/EM_A[15:0]
Defaults to powered up for NOR boot.
PCI/HPI/EMIFA Powerdown Control.
This bit controls the 28 pins used by PCI, HPI, or EMIFA but not shared with ATA. These pins
include: PCI_CLK/GP[10], PCI_DEVSEL/HCNTL1/EM_BA[1], PCI_FRAME/HINT/EM_BA[0],
PCI_IRDY/HRDY/EM_A[17]/(CLE), PCI_TRDY/HHWIL/EM_A[16]/(ALE),
16 PCIHPI0
PCI_STOP/HCNTL0/EM_WE, PCI_SERR/HDS1/EM_OE, PCI_PERR/HCS/EM_DQM1,
PCI_PAR/HAS/EM_DQM0, PCI_INTA/EM_WAIT2/(RDY2/BSY2), PCI_CBE3/HR/W/EM_CS3,
PCI_CBE2/HDS2/EM_CS2, PCI_AD[15:0]/HD[15:0]/EM_D[15:0]
Defaults to powered up for NOR boot.
GPIO Powerdown Control.
15 GPIO
This bit controls the eight GP[7:0] pins. Defaults to powered up.
WD Timer Powerdown Control.
14 WDTIM
This bit controls the WD Timer pin TOUT2.
Timer1 Powerdown Control.
13 TIM23
This bit controls the three Timer1 pins TINP1L, TOUT1L, and TOUT1U.
Timer0 Powerdown Control.
12 TIM01
This bit controls the four Timer0 pins TINP0L, TINP0U, TOUT0L, and TOUT0U.
PWM1 Powerdown Control.
11 PWM1
This bit controls the PWM1/TS1_DOUT pin.
PWM0 Powerdown Control.
10 PWM0
This bit controls the PWM0/CRG0_PO/TS1_ENAO pin.
UART2 Flow Control Powerdown Control.
9 UR2FC This bit controls the URTS2/UIRTX2/TS0_PSTIN/GP[41] and
UCTS2/USD2/CRG0_VCXI/GP[42]/TS1_PSTO pins.
84 Device Configurations Copyright © 2009–2012, Texas Instruments Incorporated
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