Datasheet

TMS320DM6467T
www.ti.com SPRS605C –JULY 2009–REVISED JUNE 2012
Table 3-29. General Purpose Input/Output (GPIO) Terminal Functions (continued)
SIGNAL
TYPE
(1)
OTHER
(2) (3)
DESCRIPTION
NAME NO.
PCI_RSV4/
DIOW/ IPU
A11 I/O/Z
GP[20]/ DV
DD33
These pins are multiplexed between PCI, ATA, GPIO, and EMIFA.
EM_WAIT4
When 32-bit HPI mode is enabled (PINMUX0.PCIEN = 0, PINMUX0.HPIEN = 1,
PCI_RSV5/
PINMUX0.ATAEN = 0), these pins are GP[20:21] (I/0/Z).
IORDY/ IPU
D11 I/O/Z
GP[21]/ DV
DD33
EM_WAIT3
USB_DRVVBUS/ IPD This pin is multiplexed between USB and GPIO.
B18 I/O/Z
GP[22] DV
DD33
When not used for USB (PINMUX0.VBUSDIS = 1), this pin is GP[22] (I/O/Z).
URXD1/ This pin is multiplexed between UART1, TSIF0, and GPIO.
IPD
TS0_DIN7/ Y18 I/O/Z When UART1 GPIO muxing is selected (PINMUX1.UART1CTL = 11) and TSIF0
DV
DD33
GP[23] serial input is not enabled (PINMUX0.PTSIMUX ≠ 11), this pin is GP[23] (I/O/Z).
UTXD1/
This pin is multiplexed between UART1, TSIF0, and GPIO.
URCTX1/ IPD
AB19 I/O/Z When UART1 GPIO muxing is selected (PINMUX1. UART1CTL = 11) and TSIF0
TS0_DOUT7/ DV
DD33
serial input is not enabled (PINMUX0.PTSIMUX ≠ 11), this pin is GP[24] (I/O/Z).
GP[24]
URTS1/
UIRTX1/ IPD
AA18 I/O/Z
TS0_WAITO/ DV
DD33
These pins are multiplexed between UART1, TSIF0, and GPIO.
GP[25]
When UART1 GPIO muxing is selected (PINMUX1.UART1CTL = 11) and TSIF0
input is not enabled (PINMUX0.PTSIMUX = 0x), these pins are GP[25:26] (I/O/Z).
UCTS1/USD1/
IPU
TS0_EN_WAITO/ Y17 I/O/Z
DV
DD33
GP[26]
GP[27:31] n/a – – GP[27:31] are not pinned out on this device.
PCI_CBE1/
ATA_CS1/ IPU
C2 I/O/Z
GP[32]/ DV
DD33
These pins are multiplexed between PCI, ATA, GPIO, and EMIFA.
EM_A[19]
When 32-bit HPI mode is enabled (PINMUX0.PCIEN = 0, PINMUX0.HPIEN = 1,
PCI_CBE0/
PINMUX0.ATAEN = 0), these pins are GP[32:33] (I/O/Z).
ATA_CS0/ IPU
F4 I/O/Z
GP[33]/ DV
DD33
EM_A[18]
GP[34:35] n/a – – GP[34:35] are not pinned out on this device.
UDTR0/
IPU
TS0_ENAO/ Y12 I/O/Z
DV
DD33
GP[36]
These pins are multiplexed between UART0, TSIF0, and GPIO.
UDSR0/
IPU When UART0 UART with modem functional muxing is not selected
TS0_PSTO/ AB11 I/O/Z
DV
DD33
(PINMUX1.UART0CTL ≠ 00) and TSIF0 output muxing is not enabled
GP[37]
(PINMUX0.PTSOMUX ≠ 1x), these pins are GP[36:38] (I/O/Z).
UDCD0/
IPU
TS0_WAITIN/ AA11 I/O/Z
DV
DD33
GP[38]
URXD2/
CRG1_VCXI/ IPD
AB20 I/O/Z
GP[39]/ DV
DD33
These pins are multiplexed between UART2, CRGEN1, GPIO, and CRGEN0.
CRG0_VCXI
When UART2 UART GPIO muxing is selected (PINMUX1.UART2CTL = 11) and
CRGEN0/1 are not enabled (PINMUX0.CRGMUX ≠ x01, 110), these pins are
UTXD2/URCTX2/
GP[39:40] (I/O/Z).
CRG1_PO/ IPD
AA19 I/O/Z
GP[40]/ DV
DD33
CRG0_PO
This pin is multiplexed between UART2, TSIF0, and GPIO.
URTS2/UIRTX2/
IPU When UART2 UART without flow control or GPIO muxing is selected
TS0_PSTIN/ AC20 I/O/Z
DV
DD33
(PINMUX1.UART2CTL = x1) and TSIF0 input is not enabled
GP[41]
(PINMUX0.PTSIMUX = 0x), this pin is GP[41] (I/O/Z).
This pin is multiplexed between UART2, CRGEN0, GPIO, and TSIF1.
UCTS2/USD2/
When UART2 UART without flow control or GPIO muxing is selected
CRG0_VCXI/ IPU
AC21 I/O/Z (PINMUX1.UART2CTL = x1) and CRGEN0 on UART2/PWM muxing is not enabled
GP[42]/ DV
DD33
(PINMUX0.CRGMUX ≠ 10x) and TSIF1 output is not enabled
TS1_PSTO
(PINMUX0.TSSOMUX = 0x), this pin is GP[42] (I/O/Z).
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