Datasheet

TMS320DM6467T
SPRS605C –JULY 2009–REVISED JUNE 2012 www.ti.com
Table 3-29. General Purpose Input/Output (GPIO) Terminal Functions
SIGNAL
TYPE
(1)
OTHER
(2) (3)
DESCRIPTION
NAME NO.
GPIO
The DM6467T device does not support GP[47:43], GP[35:34], GP[31:27], GP[15:14], and GP[9] signals (not pinned out).
GP[7:0] pins have dedicated ARM926 and DSP interrupts.
When PCI is used, GP[19:16] pins are reserved.
IPD
GP[0] W5 I/O/Z GP[0] (I/O/Z). This pin is general-purpose input/output 0.
DV
DD33
IPD
GP[1] V5 I/O/Z GP[1] (I/O/Z). This pin is general-purpose input/output 1.
DV
DD33
GP[2]/ IPD This pin is multiplexed between GPIO and the audio clock selector.
AA4 I/O/Z
AUDIO_CLK1 DV
DD33
When audio clock 1 is disabled (PINMUX0.AUDCK1 = 0), this pin is GP[2] (I/O/Z).
GP[3]/ IPD This pin is multiplexed between GPIO and the audio clock selector.
AB3 I/O/Z
AUDIO_CLK0 DV
DD33
When audio clock 0 is disabled (PINMUX0.AUDCK0 = 0), this pin is GP[3] (I/O/Z).
This pin is multiplexed between GPIO and the TSIF clock selector.
GP[4]/ IPD
AC3 I/O/Z When the STC source clock input is disabled (PINMUX0.STCCK = 0), this pin is
STC_CLKIN DV
DD33
GP[4] (I/O/Z).
IPD
GP[5] B11 I/O/Z This pin is GP[5] (I/O/Z).
DV
DD33
IPD
GP[6] E11 I/O/Z This pin is GP[6] (I/O/Z).
DV
DD33
IPD
GP[7] A12 I/O/Z This pin is GP[7] (I/O/Z).
DV
DD33
This pin is multiplexed between UART0, GPIO, and TSIF1.
URIN0/GP[8]/ IPD When UART0 UART with modem functional muxing is not selected
Y11 I/O/Z
TS1_WAITIN DV
DD33
(PINMUX1.UART0CTL = 00) and TSIF1 output on UART/PWM muxing is not
enabled (PINMUX0.TSSOMUX ≠ 11), this pin is GP[8] (I/O/Z).
GP[9] n/a – – GP[9] is not pinned out on this device.
IPU This pin is multiplexed between PCI and GPIO.
PCI_CLK/GP[10] A10 I/O/Z
DV
DD33
When PCI is disabled (PINMUX0.PCIEN = 0), this pin is GP[10] (I/O/Z).
PCI_REQ/ This pin is multiplexed between PCI, ATA, GPIO, and EMIFA.
IPU
DMARQ/ B9 I/O/Z When 32-bit HPI mode is enabled (PINMUX0.PCIEN = 0, PINMUX0.HPIEN = 1,
DV
DD33
GP[11]/EM_CS5 PINMUX0.ATAEN = 0), this pin is GP[11] (I/O/Z).
PCI_GNT/ This pin is multiplexed between PCI, ATA, GPIO, and EMIFA.
IPU
DMACK/ D10 I/O/Z When 32-bit HPI mode is enabled (PINMUX0.PCIEN = 0, PINMUX0.HPIEN = 1,
DV
DD33
GP[12]/EM_CS4 PINMUX0.ATAEN = 0), this pin is GP[12] (I/O/Z).
PCI_RST/ This pin is multiplexed between PCI, ATA, GPIO, and EMIFA.
IPD
DA2/ C10 I/O/Z When 32-bit HPI mode is enabled (PINMUX0.PCIEN = 0, PINMUX0.HPIEN = 1,
DV
DD33
GP[13]/EM_A[22] PINMUX0.ATAEN = 0), this pin is GP[13] (I/O/Z).
GP[14:15] n/a – – GP[14:15] are not pinned out on this device.
PCI_RSV0/DA1/
IPD
GP[16]/ A9 I/O/Z
DV
DD33
EM_A[21]
PCI_RSV1/DA0/ IPD
E9 I/O/Z
GP[17]/EM_A[20] DV
DD33
These pins are multiplexed between PCI, ATA, GPIO, and EMIFA.
When 32-bit HPI mode is enabled (PINMUX0.PCIEN = 0, PINMUX0.HPIEN = 1,
PCI_RSV2/
PINMUX0.ATAEN = 0), these pins are GP[16:19] (I/0/Z). When PCI mode is enabled
INTRQ/ IPD
B10 I/O/Z
(PINMUX0.PCIEN = 1), these pins are reserved.
GP[18]/ DV
DD33
EM_RSV0
PCI_RSV3/DIOR/
IPU
GP[19]/ E10 I/O/Z
DV
DD33
EM_WAIT5
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 4.8.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
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