Datasheet
Table Of Contents
- 1 Digital Media System-on-Chip (DMSoC)
- Table of Contents
- 2 Revision History
- 3 Device Overview
- 3.1 Device Characteristics
- 3.2 Device Compatibility
- 3.3 ARM Subsystem
- 3.3.1 ARM926EJ-S RISC CPU
- 3.3.2 CP15
- 3.3.3 MMU
- 3.3.4 Caches and Write Buffer
- 3.3.5 Tightly Coupled Memory (TCM)
- 3.3.6 Advanced High-Performance Bus (AHB)
- 3.3.7 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)
- 3.3.8 ARM Memory Mapping
- 3.3.9 Peripherals
- 3.3.10 PLL Controller (PLLC)
- 3.3.11 Power and Sleep Controller (PSC)
- 3.3.12 ARM Interrupt Controller (AINTC)
- 3.3.13 System Module
- 3.3.14 Power Management
- 3.4 DSP Subsystem
- 3.5 Memory Map Summary
- 3.6 Pin Assignments
- 3.7 Terminal Functions
- 3.8 Device Support
- 3.9 Documentation Support
- 3.10 Community Resources
- 4 Device Configurations
- 4.1 System Module Registers
- 4.2 Power Considerations
- 4.3 Clock Considerations
- 4.4 Boot Sequence
- 4.5 Configurations At Reset
- 4.6 Configurations After Reset
- 4.7 Multiplexed Pin Configurations
- 4.7.1 Pin Muxing Selection At Reset
- 4.7.2 Pin Muxing Selection After Reset
- 4.7.3 Pin Multiplexing Details
- 4.7.3.1 PCI, HPI, EMIFA, and ATA Pin Muxing
- 4.7.3.2 PWM Signal Muxing
- 4.7.3.3 TSIF0 Input Signal Muxing (Serial/Parallel)
- 4.7.3.4 TSIF0 Output Signal Muxing (Serial/Parallel)
- 4.7.3.5 TSIF1 Input Signal Muxing (Serial Only)
- 4.7.3.6 TSIF1 Output Signal Muxing (Serial Only)
- 4.7.3.7 CRGEN Signal Muxing
- 4.7.3.8 UART0 Pin Muxing
- 4.7.3.9 UART1 Pin Muxing
- 4.7.3.10 UART2 Pin Muxing
- 4.7.3.11 ARM/DSP Communications Interrupts
- 4.7.3.12 Emulation Control
- 4.8 Debugging Considerations
- 5 System Interconnect
- 6 Device Operating Conditions
- 7 Peripheral Information and Electrical Specifications
- 7.1 Parameter Information
- 7.2 Recommended Clock and Control Signal Transition Behavior
- 7.3 Power Supplies
- 7.4 External Clock Input From DEV_MXI/DEV_CLKIN and AUX_MXI/AUX_CLKIN Pins
- 7.5 Clock PLLs
- 7.6 Enhanced Direct Memory Access (EDMA3) Controller
- 7.7 Reset
- 7.8 Interrupts
- 7.9 External Memory Interface (EMIF)
- 7.10 DDR2 Memory Controller
- 7.10.1 DDR2 Memory Controller Electrical Data/Timing
- 7.10.2 DDR2 Interface
- 7.10.2.1 DDR2 Interface Schematic
- 7.10.2.2 Compatible JEDEC DDR2 Devices
- 7.10.2.3 PCB Stackup
- 7.10.2.4 Placement
- 7.10.2.5 DDR2 Keep Out Region
- 7.10.2.6 Bulk Bypass Capacitors
- 7.10.2.7 High-Speed Bypass Capacitors
- 7.10.2.8 Net Classes
- 7.10.2.9 DDR2 Signal Termination
- 7.10.2.10 VREF Routing
- 7.10.2.11 DDR2 CK and ADDR_CTRL Routing
- 7.11 Video Port Interface (VPIF)
- 7.12 Transport Stream Interface (TSIF)
- 7.13 Clock Recovery Generator (CRGEN)
- 7.14 Video Data Conversion Engine (VDCE)
- 7.15 Peripheral Component Interconnect (PCI)
- 7.16 Ethernet MAC (EMAC)
- 7.17 Management Data Input/Output (MDIO)
- 7.18 Host-Port Interface (HPI) Peripheral
- 7.19 USB 2.0 [see Note]
- 7.20 ATA Controller
- 7.21 VLYNQ
- 7.22 Multichannel Audio Serial Port (McASP0/1) Peripherals
- 7.23 Serial Peripheral Interface (SPI)
- 7.24 Universal Asynchronouse Receiver/Transmitter (UART)
- 7.25 Inter-Integrated Circuit (I2C)
- 7.26 Pulse Width Modulator (PWM)
- 7.27 Timers
- 7.28 General-Purpose Input/Output (GPIO)
- 7.29 IEEE 1149.1 JTAG
- 8 Mechanical Packaging and Orderable Information
TMS320DM6467T
SPRS605C –JULY 2009–REVISED JUNE 2012
www.ti.com
Table 3-23. UART0 Terminal Functions
SIGNAL
TYPE
(1)
OTHER
(2) (3)
DESCRIPTION
NAME NO.
Actual UART0 pin functions are determined by the PINMUX0 and PINMUX1 register bit settings. For more details, see
Section 4.7.3, Pin Multiplexing.
UART0 WITH MODEM CONTROL (PINMUX1.UART0CTL = 00)
This pin is multiplexed between UART0 and TSIF1.
URXD0/ IPD When UART0 UART functional muxing is selected (PINMUX1.UART0CTL = 0x)
AB13 I
TS1_DIN DV
DD33
and TSIF1 input on UART0 muxing is not enabled (PINMUX0.TSSIMUX ≠ 01), this
pin is UART0 receive data, URXD0 (I).
This pin is multiplexed between UART0 and TSIF1.
UTXD0/
IPD When UART0 UART functional muxing is selected (PINMUX1.UART0CTL = 0x)
URCTX0/ Y13 I/O/Z
DV
DD33
and TSIF1 input on UART0 muxing is not enabled (PINMUX0.TSSIMUX ≠ 01), this
TS1_PSTIN
pin is UART0 transmit data, UTXD0 (O/Z).
This pin is multiplexed between UART0 and TSIF1.
URTS0 /
IPU When UART0 UART functional muxing is selected (PINMUX1.UART0CTL = 0x)
UIRTX0/ AA13 I/O/Z
DV
DD33
and TSIF1 input on UART0 muxing is not enabled (PINMUX0.TSSIMUX ≠ 01), this
TS1_EN_WAITO
pin is the UART0 request-to-send signal, URTS0 (O/Z).
This pin is multiplexed between UART0 and TSIF1.
IPU When UART0 UART functional muxing is selected (PINMUX1.UART0CTL = 0x)
UCTS0 / USD0 AC12 I/O/Z
DV
DD33
and TSIF1 input on UART0 muxing is not enabled (PINMUX0.TSSIMUX ≠ 01), this
pin is the UART0 clear-to-send signal, UCTS0 (I).
This pin is multiplexed between UART0, TSIF0, and GPIO.
UDTR0 /
IPU When UART0 UART with modem functional muxing is selected
TS0_ENAO/ Y12 I/O/Z
DV
DD33
(PINMUX1.UART0CTL = 00) and TSIF0 output muxing is not enabled
GP[36]
(PINMUX0.PTSOMUX ≠ 1x), this pin is UART0 data-terminal-ready, UDTR0 (O/Z).
This pin is multiplexed between UART0, TSIF0, and GPIO.
UDSR0 /
IPU When UART0 UART with modem functional muxing is selected
TS0_PSTO/ AB11 I/O/Z
DV
DD33
(PINMUX1.UART0CTL = 00) and TSIF0 output muxing is not enabled
GP[37]
(PINMUX0.PTSOMUX ≠ 1x), this pin is UART0 data-set-ready, UDSR0 (I).
This pin is multiplexed between UART0, TSIF0, and GPIO.
UDCD0 /
IPU When UART0 UART with modem functional muxing is selected
TS0_WAITIN/ AA11 I/O/Z
DV
DD33
(PINMUX1.UART0CTL = 00) and TSIF0 output muxing is not enabled
GP[38]
(PINMUX0.PTSOMUX ≠ 1x), this pin is UART0 data-carrier-detect, UDCD0 (I).
This pin is multiplexed between UART0, GPIO, and TSIF1.
When UART0 UART with modem functional muxing is selected
URIN0 /GP[8]/ IPD
Y11 I/O/Z (PINMUX1.UART0CTL = 00) and TSIF1 output on UART/PWM muxing is not
TS1_WAITIN DV
DD33
enabled (PINMUX0.TSSOMUX ≠ 11), this pin is the UART0 ring indicator,
URIN0 (I).
UART0 WITHOUT MODEM CONTROL (PINMUX1.UART0CTL = 01)
This pin is multiplexed between UART0 and TSIF1.
URXD0/ IPD When UART0 UART functional muxing is selected (PINMUX1.UART0CTL = 0x)
AB13 I
TS1_DIN DV
DD33
and TSIF1 input on UART0 muxing is not enabled (PINMUX0.TSSIMUX ≠ 01), this
pin is UART0 receive data, URXD0 (I).
This pin is multiplexed between UART0 and TSIF1.
UTXD0/
IPD When UART0 UART functional muxing is selected (PINMUX1.UART0CTL = 0x)
URCTX0/ Y13 I/O/Z
DV
DD33
and TSIF1 input on UART0 muxing is not enabled (PINMUX0.TSSIMUX ≠ 01), this
TS1_PSTIN
pin is UART0 transmit data, UTXD0 (O/Z).
This pin is multiplexed between UART0 and TSIF1.
URTS0 /
IPU When UART0 UART functional muxing is selected (PINMUX1.UART0CTL = 0x)
UIRTX0/ AA13 I/O/Z
DV
DD33
and TSIF1 input on UART0 muxing is not enabled (PINMUX0.TSSIMUX ≠ 01), this
TS1_EN_WAITO
pin is UART0 request-to-send signal, URTS0 (O/Z).
When UART0 UART functional muxing is selected (PINMUX1.UART0CTL = 0x)
UCTS0 / IPU
AC12 I/O/Z and TSIF1 input on UART0 muxing is not enabled (PINMUX0.TSSIMUX ≠ 01), this
USD0 DV
DD33
pin is UART0 clear-to-send signal, UCTS0 (I).
(1) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 4.8.1, Pullup/Pulldown Resistors.
(2) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(3) Specifies the operating I/O supply voltage for each signal
60 Device Overview Copyright © 2009–2012, Texas Instruments Incorporated
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