Datasheet
Table Of Contents
- 1 Digital Media System-on-Chip (DMSoC)
- Table of Contents
- 2 Revision History
- 3 Device Overview
- 3.1 Device Characteristics
- 3.2 Device Compatibility
- 3.3 ARM Subsystem
- 3.3.1 ARM926EJ-S RISC CPU
- 3.3.2 CP15
- 3.3.3 MMU
- 3.3.4 Caches and Write Buffer
- 3.3.5 Tightly Coupled Memory (TCM)
- 3.3.6 Advanced High-Performance Bus (AHB)
- 3.3.7 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)
- 3.3.8 ARM Memory Mapping
- 3.3.9 Peripherals
- 3.3.10 PLL Controller (PLLC)
- 3.3.11 Power and Sleep Controller (PSC)
- 3.3.12 ARM Interrupt Controller (AINTC)
- 3.3.13 System Module
- 3.3.14 Power Management
- 3.4 DSP Subsystem
- 3.5 Memory Map Summary
- 3.6 Pin Assignments
- 3.7 Terminal Functions
- 3.8 Device Support
- 3.9 Documentation Support
- 3.10 Community Resources
- 4 Device Configurations
- 4.1 System Module Registers
- 4.2 Power Considerations
- 4.3 Clock Considerations
- 4.4 Boot Sequence
- 4.5 Configurations At Reset
- 4.6 Configurations After Reset
- 4.7 Multiplexed Pin Configurations
- 4.7.1 Pin Muxing Selection At Reset
- 4.7.2 Pin Muxing Selection After Reset
- 4.7.3 Pin Multiplexing Details
- 4.7.3.1 PCI, HPI, EMIFA, and ATA Pin Muxing
- 4.7.3.2 PWM Signal Muxing
- 4.7.3.3 TSIF0 Input Signal Muxing (Serial/Parallel)
- 4.7.3.4 TSIF0 Output Signal Muxing (Serial/Parallel)
- 4.7.3.5 TSIF1 Input Signal Muxing (Serial Only)
- 4.7.3.6 TSIF1 Output Signal Muxing (Serial Only)
- 4.7.3.7 CRGEN Signal Muxing
- 4.7.3.8 UART0 Pin Muxing
- 4.7.3.9 UART1 Pin Muxing
- 4.7.3.10 UART2 Pin Muxing
- 4.7.3.11 ARM/DSP Communications Interrupts
- 4.7.3.12 Emulation Control
- 4.8 Debugging Considerations
- 5 System Interconnect
- 6 Device Operating Conditions
- 7 Peripheral Information and Electrical Specifications
- 7.1 Parameter Information
- 7.2 Recommended Clock and Control Signal Transition Behavior
- 7.3 Power Supplies
- 7.4 External Clock Input From DEV_MXI/DEV_CLKIN and AUX_MXI/AUX_CLKIN Pins
- 7.5 Clock PLLs
- 7.6 Enhanced Direct Memory Access (EDMA3) Controller
- 7.7 Reset
- 7.8 Interrupts
- 7.9 External Memory Interface (EMIF)
- 7.10 DDR2 Memory Controller
- 7.10.1 DDR2 Memory Controller Electrical Data/Timing
- 7.10.2 DDR2 Interface
- 7.10.2.1 DDR2 Interface Schematic
- 7.10.2.2 Compatible JEDEC DDR2 Devices
- 7.10.2.3 PCB Stackup
- 7.10.2.4 Placement
- 7.10.2.5 DDR2 Keep Out Region
- 7.10.2.6 Bulk Bypass Capacitors
- 7.10.2.7 High-Speed Bypass Capacitors
- 7.10.2.8 Net Classes
- 7.10.2.9 DDR2 Signal Termination
- 7.10.2.10 VREF Routing
- 7.10.2.11 DDR2 CK and ADDR_CTRL Routing
- 7.11 Video Port Interface (VPIF)
- 7.12 Transport Stream Interface (TSIF)
- 7.13 Clock Recovery Generator (CRGEN)
- 7.14 Video Data Conversion Engine (VDCE)
- 7.15 Peripheral Component Interconnect (PCI)
- 7.16 Ethernet MAC (EMAC)
- 7.17 Management Data Input/Output (MDIO)
- 7.18 Host-Port Interface (HPI) Peripheral
- 7.19 USB 2.0 [see Note]
- 7.20 ATA Controller
- 7.21 VLYNQ
- 7.22 Multichannel Audio Serial Port (McASP0/1) Peripherals
- 7.23 Serial Peripheral Interface (SPI)
- 7.24 Universal Asynchronouse Receiver/Transmitter (UART)
- 7.25 Inter-Integrated Circuit (I2C)
- 7.26 Pulse Width Modulator (PWM)
- 7.27 Timers
- 7.28 General-Purpose Input/Output (GPIO)
- 7.29 IEEE 1149.1 JTAG
- 8 Mechanical Packaging and Orderable Information
TMS320DM6467T
SPRS605C –JULY 2009–REVISED JUNE 2012
www.ti.com
7.2 Recommended Clock and Control Signal Transition
1 Digital Media System-on-Chip (DMSoC) ............ 1
Behavior ........................................... 140
1.1 Features ............................................. 1
7.3 Power Supplies .................................... 141
1.2 Description ........................................... 3
7.4 External Clock Input From DEV_MXI/DEV_CLKIN
1.3 Functional Block Diagram ........................... 5
and AUX_MXI/AUX_CLKIN Pins .................. 149
2 Revision History ........................................ 7
7.5 Clock PLLs ........................................ 153
3 Device Overview ........................................ 8
7.6 Enhanced Direct Memory Access (EDMA3)
3.1 Device Characteristics ............................... 8
Controller .......................................... 162
3.2 Device Compatibility ................................ 10
7.7 Reset .............................................. 182
3.3 ARM Subsystem .................................... 10
7.8 Interrupts .......................................... 193
3.4 DSP Subsystem .................................... 14
7.9 External Memory Interface (EMIF) ................ 199
3.5 Memory Map Summary ............................ 19
7.10 DDR2 Memory Controller ......................... 206
3.6 Pin Assignments .................................... 23
7.11 Video Port Interface (VPIF) ....................... 219
3.7 Terminal Functions ................................. 30
7.12 Transport Stream Interface (TSIF) ................ 227
3.8 Device Support ..................................... 78
7.13 Clock Recovery Generator (CRGEN) ............. 237
3.9 Documentation Support ............................ 80
7.14 Video Data Conversion Engine (VDCE) .......... 240
3.10 Community Resources ............................. 80
7.15 Peripheral Component Interconnect (PCI) ........ 243
4 Device Configurations ................................ 81
7.16 Ethernet MAC (EMAC) ............................ 249
4.1 System Module Registers .......................... 81
7.17 Management Data Input/Output (MDIO) .......... 259
4.2 Power Considerations .............................. 83
7.18 Host-Port Interface (HPI) Peripheral .............. 261
4.3 Clock Considerations ............................... 86
7.19 USB 2.0 [see Note] ............................... 269
4.4 Boot Sequence ..................................... 93
7.20 ATA Controller ..................................... 279
4.5 Configurations At Reset ............................ 99
7.21 VLYNQ ............................................ 294
4.6 Configurations After Reset ........................ 102
7.22 Multichannel Audio Serial Port (McASP0/1)
Peripherals ........................................ 299
4.7 Multiplexed Pin Configurations .................... 110
7.23 Serial Peripheral Interface (SPI) .................. 311
4.8 Debugging Considerations ........................ 132
7.24 Universal Asynchronouse Receiver/Transmitter
5 System Interconnect ................................ 134
(UART) ............................................ 326
6 Device Operating Conditions ...................... 135
7.25 Inter-Integrated Circuit (I2C) ...................... 333
6.1 Absolute Maximum Ratings Over Operating Case
7.26 Pulse Width Modulator (PWM) .................... 337
Temperature Range (Unless Otherwise Noted) .. 135
7.27 Timers ............................................. 339
6.2 Recommended Operating Conditions ............. 136
7.28 General-Purpose Input/Output (GPIO) ............ 342
6.3 Electrical Characteristics Over Recommended
Ranges of Supply Voltage and Operating
7.29 IEEE 1149.1 JTAG ................................ 345
Temperature (Unless Otherwise Noted) .......... 137
8 Mechanical Packaging and Orderable
7 Peripheral Information and Electrical
Information ............................................ 348
Specifications ......................................... 139
8.1 Thermal Data for CUT ............................ 348
7.1 Parameter Information ............................ 139
8.2 Packaging Information ............................ 348
6 Contents Copyright © 2009–2012, Texas Instruments Incorporated
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