Datasheet
Table Of Contents
- 1 Digital Media System-on-Chip (DMSoC)
- Table of Contents
- 2 Revision History
- 3 Device Overview
- 3.1 Device Characteristics
- 3.2 Device Compatibility
- 3.3 ARM Subsystem
- 3.3.1 ARM926EJ-S RISC CPU
- 3.3.2 CP15
- 3.3.3 MMU
- 3.3.4 Caches and Write Buffer
- 3.3.5 Tightly Coupled Memory (TCM)
- 3.3.6 Advanced High-Performance Bus (AHB)
- 3.3.7 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)
- 3.3.8 ARM Memory Mapping
- 3.3.9 Peripherals
- 3.3.10 PLL Controller (PLLC)
- 3.3.11 Power and Sleep Controller (PSC)
- 3.3.12 ARM Interrupt Controller (AINTC)
- 3.3.13 System Module
- 3.3.14 Power Management
- 3.4 DSP Subsystem
- 3.5 Memory Map Summary
- 3.6 Pin Assignments
- 3.7 Terminal Functions
- 3.8 Device Support
- 3.9 Documentation Support
- 3.10 Community Resources
- 4 Device Configurations
- 4.1 System Module Registers
- 4.2 Power Considerations
- 4.3 Clock Considerations
- 4.4 Boot Sequence
- 4.5 Configurations At Reset
- 4.6 Configurations After Reset
- 4.7 Multiplexed Pin Configurations
- 4.7.1 Pin Muxing Selection At Reset
- 4.7.2 Pin Muxing Selection After Reset
- 4.7.3 Pin Multiplexing Details
- 4.7.3.1 PCI, HPI, EMIFA, and ATA Pin Muxing
- 4.7.3.2 PWM Signal Muxing
- 4.7.3.3 TSIF0 Input Signal Muxing (Serial/Parallel)
- 4.7.3.4 TSIF0 Output Signal Muxing (Serial/Parallel)
- 4.7.3.5 TSIF1 Input Signal Muxing (Serial Only)
- 4.7.3.6 TSIF1 Output Signal Muxing (Serial Only)
- 4.7.3.7 CRGEN Signal Muxing
- 4.7.3.8 UART0 Pin Muxing
- 4.7.3.9 UART1 Pin Muxing
- 4.7.3.10 UART2 Pin Muxing
- 4.7.3.11 ARM/DSP Communications Interrupts
- 4.7.3.12 Emulation Control
- 4.8 Debugging Considerations
- 5 System Interconnect
- 6 Device Operating Conditions
- 7 Peripheral Information and Electrical Specifications
- 7.1 Parameter Information
- 7.2 Recommended Clock and Control Signal Transition Behavior
- 7.3 Power Supplies
- 7.4 External Clock Input From DEV_MXI/DEV_CLKIN and AUX_MXI/AUX_CLKIN Pins
- 7.5 Clock PLLs
- 7.6 Enhanced Direct Memory Access (EDMA3) Controller
- 7.7 Reset
- 7.8 Interrupts
- 7.9 External Memory Interface (EMIF)
- 7.10 DDR2 Memory Controller
- 7.10.1 DDR2 Memory Controller Electrical Data/Timing
- 7.10.2 DDR2 Interface
- 7.10.2.1 DDR2 Interface Schematic
- 7.10.2.2 Compatible JEDEC DDR2 Devices
- 7.10.2.3 PCB Stackup
- 7.10.2.4 Placement
- 7.10.2.5 DDR2 Keep Out Region
- 7.10.2.6 Bulk Bypass Capacitors
- 7.10.2.7 High-Speed Bypass Capacitors
- 7.10.2.8 Net Classes
- 7.10.2.9 DDR2 Signal Termination
- 7.10.2.10 VREF Routing
- 7.10.2.11 DDR2 CK and ADDR_CTRL Routing
- 7.11 Video Port Interface (VPIF)
- 7.12 Transport Stream Interface (TSIF)
- 7.13 Clock Recovery Generator (CRGEN)
- 7.14 Video Data Conversion Engine (VDCE)
- 7.15 Peripheral Component Interconnect (PCI)
- 7.16 Ethernet MAC (EMAC)
- 7.17 Management Data Input/Output (MDIO)
- 7.18 Host-Port Interface (HPI) Peripheral
- 7.19 USB 2.0 [see Note]
- 7.20 ATA Controller
- 7.21 VLYNQ
- 7.22 Multichannel Audio Serial Port (McASP0/1) Peripherals
- 7.23 Serial Peripheral Interface (SPI)
- 7.24 Universal Asynchronouse Receiver/Transmitter (UART)
- 7.25 Inter-Integrated Circuit (I2C)
- 7.26 Pulse Width Modulator (PWM)
- 7.27 Timers
- 7.28 General-Purpose Input/Output (GPIO)
- 7.29 IEEE 1149.1 JTAG
- 8 Mechanical Packaging and Orderable Information
TMS320DM6467T
www.ti.com
SPRS605C –JULY 2009–REVISED JUNE 2012
Table 3-16. Video-Port Interface (VPIF) Terminal Functions
SIGNAL
TYPE
(1)
OTHER
(2) (3)
DESCRIPTION
NAME NO.
VIDEO-PORT INTERFACE (VPIF) – CAPTURE
IPD
VP_CLKIN0 AC13 I VPIF capture channel 0 input clock (I).
DV
DD33
IPD
VP_CLKIN1 AB18 I VPIF capture channel 1 input clock (I).
DV
DD33
This pin is multiplexed between the VPIF and TSIF0.
VP_DIN15_VP_VSYNC/ IPD
AC18 I When used for the VPIF, this pin is capture data bit 15 or the vertical sync
TS0_DIN7 DV
DD33
input, VP_DIN15_VSYNC (I).
This pin is multiplexed between the VPIF and TSIF0.
VP_DIN14_VP_HSYNC/ IPD
AA17 I When used for the VPIF, this pin is capture data bit 14 or the horizontal sync
TS0_DIN6 DV
DD33
input, VP_DIN14_HSYNC (I).
This pin is multiplexed between the VPIF and TSIF0.
VP_DIN13_FIELD/ IPD
AB17 I When used for the VPIF, this pin is capture data bit 13 or the field indicator
TS0_DIN5 DV
DD33
input, VP_DIN13_FIELD (I).
VP_DIN12/
AC17
TS0_DIN4
VP_DIN11/
Y16
TS0_DIN3
VP_DIN10/ IPD These pins are multiplexed between the VPIF and TSIF0.
AA16 I
TS0_DIN2 DV
DD33
When used for the VPIF, these pins are capture data bits, VP_DIN[12:8] (I).
VP_DIN9/
AB16
TS0_DIN1
VP_DIN8/
AC16
TS0_DIN0
VP_DIN7/
TS0_DOUT7/ Y14
TS1_DIN
VP_DIN6/
TS0_DOUT6/ AA14
TS1_PSTIN
IPD These pins are multiplexed between the VPIF, TSIF0, and TSIF1.
I/O/Z
DV
DD33
When used for the VPIF, these pins are capture data bits, VP_DIN[7:4] (I).
VP_DIN5/
TS0_DOUT5/ AB14
TS1_EN_WAITO
VP_DIN4/
TS0_DOUT4/ AC14
TS1_WAITO
VP_DIN3/
Y15
TS0_DOUT3
VP_DIN2/
AA15
TS0_DOUT2
IPD These pins are multiplexed between the VPIF and TSIF0.
I/O/Z
DV
DD33
When used for the VPIF, these pins are capture data bits, VP_DIN[3:0] (I).
VP_DIN1/
AB15
TS0_DOUT1
VP_DIN0/
AC15
TS0_DOUT0
VIDEO-PORT INTERFACE (VPIF) – DISPLAY
IPD
VP_CLKIN2 Y10 I VPIF display channel 2 source input clock (I).
DV
DD33
This pin is multiplexed between the VPIF and TSIF1.
VP_CLKIN3/ IPD
AC9 I/O/Z When used for VPIF, this pin is display channel 3 source clock, VP_CLKIN3
TS1_CLKO DV
DD33
(I).
-
VP_CLKO2 AA9 O/Z VPIF display channel 2 output clock (O/Z).
DV
DD33
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 4.8.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
Copyright © 2009–2012, Texas Instruments Incorporated Device Overview 51
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