Datasheet
Table Of Contents
- 1 Digital Media System-on-Chip (DMSoC)
- Table of Contents
- 2 Revision History
- 3 Device Overview
- 3.1 Device Characteristics
- 3.2 Device Compatibility
- 3.3 ARM Subsystem
- 3.3.1 ARM926EJ-S RISC CPU
- 3.3.2 CP15
- 3.3.3 MMU
- 3.3.4 Caches and Write Buffer
- 3.3.5 Tightly Coupled Memory (TCM)
- 3.3.6 Advanced High-Performance Bus (AHB)
- 3.3.7 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)
- 3.3.8 ARM Memory Mapping
- 3.3.9 Peripherals
- 3.3.10 PLL Controller (PLLC)
- 3.3.11 Power and Sleep Controller (PSC)
- 3.3.12 ARM Interrupt Controller (AINTC)
- 3.3.13 System Module
- 3.3.14 Power Management
- 3.4 DSP Subsystem
- 3.5 Memory Map Summary
- 3.6 Pin Assignments
- 3.7 Terminal Functions
- 3.8 Device Support
- 3.9 Documentation Support
- 3.10 Community Resources
- 4 Device Configurations
- 4.1 System Module Registers
- 4.2 Power Considerations
- 4.3 Clock Considerations
- 4.4 Boot Sequence
- 4.5 Configurations At Reset
- 4.6 Configurations After Reset
- 4.7 Multiplexed Pin Configurations
- 4.7.1 Pin Muxing Selection At Reset
- 4.7.2 Pin Muxing Selection After Reset
- 4.7.3 Pin Multiplexing Details
- 4.7.3.1 PCI, HPI, EMIFA, and ATA Pin Muxing
- 4.7.3.2 PWM Signal Muxing
- 4.7.3.3 TSIF0 Input Signal Muxing (Serial/Parallel)
- 4.7.3.4 TSIF0 Output Signal Muxing (Serial/Parallel)
- 4.7.3.5 TSIF1 Input Signal Muxing (Serial Only)
- 4.7.3.6 TSIF1 Output Signal Muxing (Serial Only)
- 4.7.3.7 CRGEN Signal Muxing
- 4.7.3.8 UART0 Pin Muxing
- 4.7.3.9 UART1 Pin Muxing
- 4.7.3.10 UART2 Pin Muxing
- 4.7.3.11 ARM/DSP Communications Interrupts
- 4.7.3.12 Emulation Control
- 4.8 Debugging Considerations
- 5 System Interconnect
- 6 Device Operating Conditions
- 7 Peripheral Information and Electrical Specifications
- 7.1 Parameter Information
- 7.2 Recommended Clock and Control Signal Transition Behavior
- 7.3 Power Supplies
- 7.4 External Clock Input From DEV_MXI/DEV_CLKIN and AUX_MXI/AUX_CLKIN Pins
- 7.5 Clock PLLs
- 7.6 Enhanced Direct Memory Access (EDMA3) Controller
- 7.7 Reset
- 7.8 Interrupts
- 7.9 External Memory Interface (EMIF)
- 7.10 DDR2 Memory Controller
- 7.10.1 DDR2 Memory Controller Electrical Data/Timing
- 7.10.2 DDR2 Interface
- 7.10.2.1 DDR2 Interface Schematic
- 7.10.2.2 Compatible JEDEC DDR2 Devices
- 7.10.2.3 PCB Stackup
- 7.10.2.4 Placement
- 7.10.2.5 DDR2 Keep Out Region
- 7.10.2.6 Bulk Bypass Capacitors
- 7.10.2.7 High-Speed Bypass Capacitors
- 7.10.2.8 Net Classes
- 7.10.2.9 DDR2 Signal Termination
- 7.10.2.10 VREF Routing
- 7.10.2.11 DDR2 CK and ADDR_CTRL Routing
- 7.11 Video Port Interface (VPIF)
- 7.12 Transport Stream Interface (TSIF)
- 7.13 Clock Recovery Generator (CRGEN)
- 7.14 Video Data Conversion Engine (VDCE)
- 7.15 Peripheral Component Interconnect (PCI)
- 7.16 Ethernet MAC (EMAC)
- 7.17 Management Data Input/Output (MDIO)
- 7.18 Host-Port Interface (HPI) Peripheral
- 7.19 USB 2.0 [see Note]
- 7.20 ATA Controller
- 7.21 VLYNQ
- 7.22 Multichannel Audio Serial Port (McASP0/1) Peripherals
- 7.23 Serial Peripheral Interface (SPI)
- 7.24 Universal Asynchronouse Receiver/Transmitter (UART)
- 7.25 Inter-Integrated Circuit (I2C)
- 7.26 Pulse Width Modulator (PWM)
- 7.27 Timers
- 7.28 General-Purpose Input/Output (GPIO)
- 7.29 IEEE 1149.1 JTAG
- 8 Mechanical Packaging and Orderable Information
TMS320DM6467T
SPRS605C –JULY 2009–REVISED JUNE 2012
www.ti.com
Table 3-14. HPI Terminal Functions (continued)
SIGNAL
TYPE
(1)
OTHER
(2) (3)
DESCRIPTION
NAME NO.
PCI_AD23/
DD7/ B5
HD23/EM_A[7]
PCI_AD22/
DD6/ C7
HD22/EM_A[6]
PCI_AD21/
DD5/ C5
HD21/EM_A[5]
PCI_AD20/
DD4/ D7
These pins are multiplexed between PCI, ATA, HPI, and EMIFA.
HD20/EM_A[4]
IPD
I/O/Z In HPI-32 mode, these pins are the HPI upper data bus, HD[31:16] (I/O/Z).
DV
DD33
PCI_AD19/
In HPI-16 mode, the HD[31:16] pins are not used by the HPI .
DD3/ A4
HD19/EM_A[3]
PCI_AD18/
DD2/ E7
HD18/EM_A[2]
PCI_AD17/
DD1/ B4
HD17/EM_A[1]
PCI_AD16/
DD0/ C6
HD16/EM_A[0]
PCI_AD15/
E5
HD15/EM_D15
PCI_AD14/
C1
HD14/EM_D14
PCI_AD13/
E4
HD13/EM_D13
PCI_AD12/
D3
These pins are multiplexed between PCI, HPI, and EMIFA.
HD12/EM_D12
IPD
I/O/Z In HPI-16 mode, these pins are the HPI data bus, HD[15:0] (I/O/Z).
DV
DD33
PCI_AD11/
In HPI-32 mode, these pins are the HPI lower data bus, HD[15:0] (I/O/Z).
E3
HD11/EM_D11
PCI_AD10/
D2
HD10/EM_D10
PCI_AD9/
F5
HD9/EM_D9
PCI_AD8/
D1
HD8/EM_D8
PCI_AD7/
E2
HD7/EM_D7
PCI_AD6/
F3
HD6/EM_D6
PCI_AD5/
E1
HD5/EM_D5
PCI_AD4/
G5
These pins are multiplexed between PCI, HPI, and EMIFA.
HD4/EM_D4
IPD
I/O/Z In HPI-16 mode, these pins are the HPI data bus, HD[15:0] (I/O/Z).
DV
DD33
PCI_AD3/
In HPI-32 mode, these pins are the HPI lower data bus, HD[15:0] (I/O/Z).
F2
HD3/EM_D3
PCI_AD2/
G4
HD2/EM_D2
PCI_AD1/
F1
HD1/EM_D1
PCI_AD0/
G3
HD0/EM_D0
48 Device Overview Copyright © 2009–2012, Texas Instruments Incorporated
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