Datasheet
Table Of Contents
- 1 Digital Media System-on-Chip (DMSoC)
- Table of Contents
- 2 Revision History
- 3 Device Overview
- 3.1 Device Characteristics
- 3.2 Device Compatibility
- 3.3 ARM Subsystem
- 3.3.1 ARM926EJ-S RISC CPU
- 3.3.2 CP15
- 3.3.3 MMU
- 3.3.4 Caches and Write Buffer
- 3.3.5 Tightly Coupled Memory (TCM)
- 3.3.6 Advanced High-Performance Bus (AHB)
- 3.3.7 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)
- 3.3.8 ARM Memory Mapping
- 3.3.9 Peripherals
- 3.3.10 PLL Controller (PLLC)
- 3.3.11 Power and Sleep Controller (PSC)
- 3.3.12 ARM Interrupt Controller (AINTC)
- 3.3.13 System Module
- 3.3.14 Power Management
- 3.4 DSP Subsystem
- 3.5 Memory Map Summary
- 3.6 Pin Assignments
- 3.7 Terminal Functions
- 3.8 Device Support
- 3.9 Documentation Support
- 3.10 Community Resources
- 4 Device Configurations
- 4.1 System Module Registers
- 4.2 Power Considerations
- 4.3 Clock Considerations
- 4.4 Boot Sequence
- 4.5 Configurations At Reset
- 4.6 Configurations After Reset
- 4.7 Multiplexed Pin Configurations
- 4.7.1 Pin Muxing Selection At Reset
- 4.7.2 Pin Muxing Selection After Reset
- 4.7.3 Pin Multiplexing Details
- 4.7.3.1 PCI, HPI, EMIFA, and ATA Pin Muxing
- 4.7.3.2 PWM Signal Muxing
- 4.7.3.3 TSIF0 Input Signal Muxing (Serial/Parallel)
- 4.7.3.4 TSIF0 Output Signal Muxing (Serial/Parallel)
- 4.7.3.5 TSIF1 Input Signal Muxing (Serial Only)
- 4.7.3.6 TSIF1 Output Signal Muxing (Serial Only)
- 4.7.3.7 CRGEN Signal Muxing
- 4.7.3.8 UART0 Pin Muxing
- 4.7.3.9 UART1 Pin Muxing
- 4.7.3.10 UART2 Pin Muxing
- 4.7.3.11 ARM/DSP Communications Interrupts
- 4.7.3.12 Emulation Control
- 4.8 Debugging Considerations
- 5 System Interconnect
- 6 Device Operating Conditions
- 7 Peripheral Information and Electrical Specifications
- 7.1 Parameter Information
- 7.2 Recommended Clock and Control Signal Transition Behavior
- 7.3 Power Supplies
- 7.4 External Clock Input From DEV_MXI/DEV_CLKIN and AUX_MXI/AUX_CLKIN Pins
- 7.5 Clock PLLs
- 7.6 Enhanced Direct Memory Access (EDMA3) Controller
- 7.7 Reset
- 7.8 Interrupts
- 7.9 External Memory Interface (EMIF)
- 7.10 DDR2 Memory Controller
- 7.10.1 DDR2 Memory Controller Electrical Data/Timing
- 7.10.2 DDR2 Interface
- 7.10.2.1 DDR2 Interface Schematic
- 7.10.2.2 Compatible JEDEC DDR2 Devices
- 7.10.2.3 PCB Stackup
- 7.10.2.4 Placement
- 7.10.2.5 DDR2 Keep Out Region
- 7.10.2.6 Bulk Bypass Capacitors
- 7.10.2.7 High-Speed Bypass Capacitors
- 7.10.2.8 Net Classes
- 7.10.2.9 DDR2 Signal Termination
- 7.10.2.10 VREF Routing
- 7.10.2.11 DDR2 CK and ADDR_CTRL Routing
- 7.11 Video Port Interface (VPIF)
- 7.12 Transport Stream Interface (TSIF)
- 7.13 Clock Recovery Generator (CRGEN)
- 7.14 Video Data Conversion Engine (VDCE)
- 7.15 Peripheral Component Interconnect (PCI)
- 7.16 Ethernet MAC (EMAC)
- 7.17 Management Data Input/Output (MDIO)
- 7.18 Host-Port Interface (HPI) Peripheral
- 7.19 USB 2.0 [see Note]
- 7.20 ATA Controller
- 7.21 VLYNQ
- 7.22 Multichannel Audio Serial Port (McASP0/1) Peripherals
- 7.23 Serial Peripheral Interface (SPI)
- 7.24 Universal Asynchronouse Receiver/Transmitter (UART)
- 7.25 Inter-Integrated Circuit (I2C)
- 7.26 Pulse Width Modulator (PWM)
- 7.27 Timers
- 7.28 General-Purpose Input/Output (GPIO)
- 7.29 IEEE 1149.1 JTAG
- 8 Mechanical Packaging and Orderable Information
TMS320DM6467T
www.ti.com
SPRS605C –JULY 2009–REVISED JUNE 2012
Table 3-14. HPI Terminal Functions
SIGNAL
TYPE
(1)
OTHER
(2) (3)
DESCRIPTION
NAME NO.
Host-Port Interface (HPI)
HPI is enabled by the PINMUX0.HPIEN =1 (and PCIEN = 0 and ATAEN dependent for 16-/32-bit modes). For more detailed information on
the HPI pin muxing, see Section 4.7.3.1, PCI, HPI, EMIFA, and ATA Pin Muxing.
PCI_PERR/
IPU This pin is multiplexed between PCI, HPI, and EMIFA.
HCS / C3 I/O/Z
DV
DD33
In HPI mode, this pin is the HPI active-low chip select input, HCS (I).
EM_DQM1
PCI_STOP/
IPU This pin is multiplexed between PCI, HPI, and EMIFA.
HCNTL0/ D5 I/O/Z
DV
DD33
In HPI mode, this pin is the HPI control input 0, HCNTL0 (I)
EM_WE
PCI_DEVSEL/
IPU This pin is multiplexed between PCI, HPI, and EMIFA.
HCNTL1/ B3 I/O/Z
DV
DD33
In HPI mode, this pin is the HPI control input 1, HCNTL1 (I).
EM_BA[1]
This pin is multiplexed between PCI, HPI, and EMIFA.
PCI_PAR/ HAS / IPU In HPI mode, this pin is the HPI address strobe, HAS (I).
D4 I/O/Z
EM_DQM0 DV
DD33
NOTE: The DM6467T HPI does not support the HAS feature. For proper HPI
operation if the pin is routed out, it must be pulled up via an external resistor.
PCI_SERR/ IPU This pin is multiplexed between PCI, HPI, and EMIFA.
B2 I/O/Z
HDS1 /EM_OE DV
DD33
In HPI mode, this pin is the HPI data strobe input 1, HDS1 (I).
PCI_CBE2/ IPU This pin is multiplexed between PCI, HPI, and EMIFA.
C4 I/O/Z
HDS2 /EM_CS2 DV
DD33
In HPI mode, this pin is the HPI data strobe input 2, HDS2 (I).
PCI_CBE3/ IPU This pin is multiplexed between PCI, HPI, and EMIFA.
A5 I/O/Z
HR/W /EM_CS3 DV
DD33
In HPI mode, this pin is the HPI host read/write select input, HR/W (I).
PCI_TRDY/
IPU This pin is multiplexed between PCI, HPI, and EMIFA.
HHWIL/ E6 I/O/Z
DV
DD33
In HPI mode, this pin is the HPI half-word identification input control, HHWIL (I).
EM_A[16]/(ALE)
PCI_AD31/
DD15/ A8
HD31/EM_A[15]
PCI_AD30/
DD14/ C9
HD30/EM_A[14]
PCI_AD29/
DD13/ B8
HD29/EM_A[13]
PCI_AD28/
DD12/ D9
These pins are multiplexed between PCI, ATA, HPI, and EMIFA.
HD28/EM_A[12]
IPD
I/O/Z In HPI-32 mode, these pins are the HPI upper data bus, HD[31:16] (I/O/Z).
DV
DD33
PCI_AD27/
In HPI-16 mode, the HD[31:16] pins are not used by the HPI .
DD11/ A6
HD27/EM_A[11]
PCI_AD26/
DD10/ C8
HD26/ EM_A[10]
PCI_AD25/
DD9/ B6
HD25/EM_A[9]
PCI_AD24/
DD8/ D8
HD24/EM_A[8]
(1) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 4.8.1, Pullup/Pulldown Resistors.
(2) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(3) Specifies the operating I/O supply voltage for each signal
Copyright © 2009–2012, Texas Instruments Incorporated Device Overview 47
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