Datasheet
Table Of Contents
- 1 Digital Media System-on-Chip (DMSoC)
- Table of Contents
- 2 Revision History
- 3 Device Overview
- 3.1 Device Characteristics
- 3.2 Device Compatibility
- 3.3 ARM Subsystem
- 3.3.1 ARM926EJ-S RISC CPU
- 3.3.2 CP15
- 3.3.3 MMU
- 3.3.4 Caches and Write Buffer
- 3.3.5 Tightly Coupled Memory (TCM)
- 3.3.6 Advanced High-Performance Bus (AHB)
- 3.3.7 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)
- 3.3.8 ARM Memory Mapping
- 3.3.9 Peripherals
- 3.3.10 PLL Controller (PLLC)
- 3.3.11 Power and Sleep Controller (PSC)
- 3.3.12 ARM Interrupt Controller (AINTC)
- 3.3.13 System Module
- 3.3.14 Power Management
- 3.4 DSP Subsystem
- 3.5 Memory Map Summary
- 3.6 Pin Assignments
- 3.7 Terminal Functions
- 3.8 Device Support
- 3.9 Documentation Support
- 3.10 Community Resources
- 4 Device Configurations
- 4.1 System Module Registers
- 4.2 Power Considerations
- 4.3 Clock Considerations
- 4.4 Boot Sequence
- 4.5 Configurations At Reset
- 4.6 Configurations After Reset
- 4.7 Multiplexed Pin Configurations
- 4.7.1 Pin Muxing Selection At Reset
- 4.7.2 Pin Muxing Selection After Reset
- 4.7.3 Pin Multiplexing Details
- 4.7.3.1 PCI, HPI, EMIFA, and ATA Pin Muxing
- 4.7.3.2 PWM Signal Muxing
- 4.7.3.3 TSIF0 Input Signal Muxing (Serial/Parallel)
- 4.7.3.4 TSIF0 Output Signal Muxing (Serial/Parallel)
- 4.7.3.5 TSIF1 Input Signal Muxing (Serial Only)
- 4.7.3.6 TSIF1 Output Signal Muxing (Serial Only)
- 4.7.3.7 CRGEN Signal Muxing
- 4.7.3.8 UART0 Pin Muxing
- 4.7.3.9 UART1 Pin Muxing
- 4.7.3.10 UART2 Pin Muxing
- 4.7.3.11 ARM/DSP Communications Interrupts
- 4.7.3.12 Emulation Control
- 4.8 Debugging Considerations
- 5 System Interconnect
- 6 Device Operating Conditions
- 7 Peripheral Information and Electrical Specifications
- 7.1 Parameter Information
- 7.2 Recommended Clock and Control Signal Transition Behavior
- 7.3 Power Supplies
- 7.4 External Clock Input From DEV_MXI/DEV_CLKIN and AUX_MXI/AUX_CLKIN Pins
- 7.5 Clock PLLs
- 7.6 Enhanced Direct Memory Access (EDMA3) Controller
- 7.7 Reset
- 7.8 Interrupts
- 7.9 External Memory Interface (EMIF)
- 7.10 DDR2 Memory Controller
- 7.10.1 DDR2 Memory Controller Electrical Data/Timing
- 7.10.2 DDR2 Interface
- 7.10.2.1 DDR2 Interface Schematic
- 7.10.2.2 Compatible JEDEC DDR2 Devices
- 7.10.2.3 PCB Stackup
- 7.10.2.4 Placement
- 7.10.2.5 DDR2 Keep Out Region
- 7.10.2.6 Bulk Bypass Capacitors
- 7.10.2.7 High-Speed Bypass Capacitors
- 7.10.2.8 Net Classes
- 7.10.2.9 DDR2 Signal Termination
- 7.10.2.10 VREF Routing
- 7.10.2.11 DDR2 CK and ADDR_CTRL Routing
- 7.11 Video Port Interface (VPIF)
- 7.12 Transport Stream Interface (TSIF)
- 7.13 Clock Recovery Generator (CRGEN)
- 7.14 Video Data Conversion Engine (VDCE)
- 7.15 Peripheral Component Interconnect (PCI)
- 7.16 Ethernet MAC (EMAC)
- 7.17 Management Data Input/Output (MDIO)
- 7.18 Host-Port Interface (HPI) Peripheral
- 7.19 USB 2.0 [see Note]
- 7.20 ATA Controller
- 7.21 VLYNQ
- 7.22 Multichannel Audio Serial Port (McASP0/1) Peripherals
- 7.23 Serial Peripheral Interface (SPI)
- 7.24 Universal Asynchronouse Receiver/Transmitter (UART)
- 7.25 Inter-Integrated Circuit (I2C)
- 7.26 Pulse Width Modulator (PWM)
- 7.27 Timers
- 7.28 General-Purpose Input/Output (GPIO)
- 7.29 IEEE 1149.1 JTAG
- 8 Mechanical Packaging and Orderable Information
TMS320DM6467T
www.ti.com
SPRS605C –JULY 2009–REVISED JUNE 2012
Table 3-10. DDR2 Memory Controller Terminal Functions
SIGNAL
TYPE
(1)
OTHER
(2) (3)
DESCRIPTION
NAME NO.
DDR2 Memory Controller
DDR_CLK M23 O/Z DV
DDR2
DDR2 Clock
DDR_CLK L23 O/Z DV
DDR2
DDR2 Differential clock
DDR_CKE M20 O/Z DV
DDR2
DDR2 Clock Enable
DDR_CS J20 O/Z DV
DDR2
DDR2 Active low chip select
DDR_WE L20 O/Z DV
DDR2
DDR2 Active low Write enable
DDR_RAS K19 O/Z DV
DDR2
DDR2 Row Access Signal output
DDR_CAS L21 O/Z DV
DDR2
DDR2 Column Access Signal output
DDR_DQM[3] V20 O/Z DV
DDR2
DDR2 Data mask outputs
DDR_DQM[3]: For upper byte data bus DDR_D[31:24]
DDR_DQM[2] Y23 O/Z DV
DDR2
DDR_DQM[2]: For DDR_D[23:16]
DDR_DQM[1] F22 O/Z DV
DDR2
DDR_DQM[1]: For DDR_D[15:8]
DDR_DQM[0]: For lower byte DDR_D[7:0]
DDR_DQM[0] F20 O/Z DV
DDR2
DDR_DQS[3] U20 I/O/Z DV
DDR2
Data strobe input/outputs for each byte of the 32-bit data bus. They are outputs to
the DDR2 memory when writing and inputs when reading. They are used to
DDR_DQS[2] V22 I/O/Z DV
DDR2
synchronize the data transfers.
DDR_DQS[1] D22 I/O/Z DV
DDR2
DDR_DQS[3] : For upper byte DDR_D[31:24]
DDR_DQS[2]: For DDR_D[23:16]
DDR_DQS[1]: For DDR_D[15:8]
DDR_DQS[0] D21 I/O/Z DV
DDR2
DDR_DQS[0]: For bottom byte DDR_D[7:0]
DDR_DQS[3] V21 I/O/Z DV
DDR2
Complimentary data strobe input/outputs for each byte of the 32-bit data bus. They
are outputs to the DDR2 memory when writing and inputs when reading. They are
DDR_DQS[2] W23 I/O/Z DV
DDR2
used to synchronize the data transfers.
DDR_DQS[1] D23 I/O/Z DV
DDR2
DDR_DQS[3] : For upper byte DDR_D[31:24]
DDR_DQS[2]: For DDR_D[23:16]
DDR_DQS[1]: For DDR_D[15:8]
DDR_DQS[0] E20 I/O/Z DV
DDR2
DDR_DQS[0]: For bottom byte DDR_D[7:0]
DDR_ODT0 K20 O/Z DV
DDR2
DDR2 on-die termination control
DDR_BA[2] P19
DDR_BA[1] M21 O/Z DV
DDR2
Bank address outputs (BA[2:0]).
DDR_BA[0] N19
DDR_A[14] N23
DDR_A[13] H21
DDR_A[12] P20
DDR_A[11] K23
DDR_A[10] T23
DDR_A[9] N22
DDR_A[8] J23
DDR_A[7] N20 O/Z DV
DDR2
DDR2 address bus
DDR_A[6] M22
DDR_A[5] N21
DDR_A[4] J22
DDR_A[3] R22
DDR_A[2] L22
DDR_A[1] R23
DDR_A[0] H23
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) Specifies the operating I/O supply voltage for each signal
(3) For more information, see the Recommended Operating Conditions table
Copyright © 2009–2012, Texas Instruments Incorporated Device Overview 39
Submit Documentation Feedback
Product Folder Link(s): TMS320DM6467T