Datasheet
Table Of Contents
- 1 Digital Media System-on-Chip (DMSoC)
- Table of Contents
- 2 Revision History
- 3 Device Overview
- 3.1 Device Characteristics
- 3.2 Device Compatibility
- 3.3 ARM Subsystem
- 3.3.1 ARM926EJ-S RISC CPU
- 3.3.2 CP15
- 3.3.3 MMU
- 3.3.4 Caches and Write Buffer
- 3.3.5 Tightly Coupled Memory (TCM)
- 3.3.6 Advanced High-Performance Bus (AHB)
- 3.3.7 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)
- 3.3.8 ARM Memory Mapping
- 3.3.9 Peripherals
- 3.3.10 PLL Controller (PLLC)
- 3.3.11 Power and Sleep Controller (PSC)
- 3.3.12 ARM Interrupt Controller (AINTC)
- 3.3.13 System Module
- 3.3.14 Power Management
- 3.4 DSP Subsystem
- 3.5 Memory Map Summary
- 3.6 Pin Assignments
- 3.7 Terminal Functions
- 3.8 Device Support
- 3.9 Documentation Support
- 3.10 Community Resources
- 4 Device Configurations
- 4.1 System Module Registers
- 4.2 Power Considerations
- 4.3 Clock Considerations
- 4.4 Boot Sequence
- 4.5 Configurations At Reset
- 4.6 Configurations After Reset
- 4.7 Multiplexed Pin Configurations
- 4.7.1 Pin Muxing Selection At Reset
- 4.7.2 Pin Muxing Selection After Reset
- 4.7.3 Pin Multiplexing Details
- 4.7.3.1 PCI, HPI, EMIFA, and ATA Pin Muxing
- 4.7.3.2 PWM Signal Muxing
- 4.7.3.3 TSIF0 Input Signal Muxing (Serial/Parallel)
- 4.7.3.4 TSIF0 Output Signal Muxing (Serial/Parallel)
- 4.7.3.5 TSIF1 Input Signal Muxing (Serial Only)
- 4.7.3.6 TSIF1 Output Signal Muxing (Serial Only)
- 4.7.3.7 CRGEN Signal Muxing
- 4.7.3.8 UART0 Pin Muxing
- 4.7.3.9 UART1 Pin Muxing
- 4.7.3.10 UART2 Pin Muxing
- 4.7.3.11 ARM/DSP Communications Interrupts
- 4.7.3.12 Emulation Control
- 4.8 Debugging Considerations
- 5 System Interconnect
- 6 Device Operating Conditions
- 7 Peripheral Information and Electrical Specifications
- 7.1 Parameter Information
- 7.2 Recommended Clock and Control Signal Transition Behavior
- 7.3 Power Supplies
- 7.4 External Clock Input From DEV_MXI/DEV_CLKIN and AUX_MXI/AUX_CLKIN Pins
- 7.5 Clock PLLs
- 7.6 Enhanced Direct Memory Access (EDMA3) Controller
- 7.7 Reset
- 7.8 Interrupts
- 7.9 External Memory Interface (EMIF)
- 7.10 DDR2 Memory Controller
- 7.10.1 DDR2 Memory Controller Electrical Data/Timing
- 7.10.2 DDR2 Interface
- 7.10.2.1 DDR2 Interface Schematic
- 7.10.2.2 Compatible JEDEC DDR2 Devices
- 7.10.2.3 PCB Stackup
- 7.10.2.4 Placement
- 7.10.2.5 DDR2 Keep Out Region
- 7.10.2.6 Bulk Bypass Capacitors
- 7.10.2.7 High-Speed Bypass Capacitors
- 7.10.2.8 Net Classes
- 7.10.2.9 DDR2 Signal Termination
- 7.10.2.10 VREF Routing
- 7.10.2.11 DDR2 CK and ADDR_CTRL Routing
- 7.11 Video Port Interface (VPIF)
- 7.12 Transport Stream Interface (TSIF)
- 7.13 Clock Recovery Generator (CRGEN)
- 7.14 Video Data Conversion Engine (VDCE)
- 7.15 Peripheral Component Interconnect (PCI)
- 7.16 Ethernet MAC (EMAC)
- 7.17 Management Data Input/Output (MDIO)
- 7.18 Host-Port Interface (HPI) Peripheral
- 7.19 USB 2.0 [see Note]
- 7.20 ATA Controller
- 7.21 VLYNQ
- 7.22 Multichannel Audio Serial Port (McASP0/1) Peripherals
- 7.23 Serial Peripheral Interface (SPI)
- 7.24 Universal Asynchronouse Receiver/Transmitter (UART)
- 7.25 Inter-Integrated Circuit (I2C)
- 7.26 Pulse Width Modulator (PWM)
- 7.27 Timers
- 7.28 General-Purpose Input/Output (GPIO)
- 7.29 IEEE 1149.1 JTAG
- 8 Mechanical Packaging and Orderable Information
TMS320DM6467T
www.ti.com
SPRS605C –JULY 2009–REVISED JUNE 2012
Table 3-9. Asynchronous External Memory Interface (EMIFA) Terminal Functions (continued)
SIGNAL
TYPE
(1)
OTHER
(2) (3)
DESCRIPTION
NAME NO.
PCI_RSV3/DIOR/ This pin is multiplexed between PCI, ATA, GPIO, and EMIFA.
IPU
GP[19]/EM_WAIT5/ E10 I/O/Z For EMIFA, this pin is wait state extension input 5 EM_WAIT5 (I).
DV
DD33
(RDY5/BSY5) When used for EMIFA (NAND), this pin is the ready/busy 5 input (RDY5/BSY5).
This pin is multiplexed between PCI, HPI, and EMIFA.
For EMIFA, this is the Bank Address 0 output EM_BA[0] (O/Z).
PCI_FRAME/
IPU When connected to a 16-bit asynchronous memory, this pin has the same
HINT/ D6 I/O/Z
DV
DD33
function as EMIF address pin 22 (EM_A[22]).
EM_BA[0]
When connected to an 8-bit asynchronous memory, this pin is the lowest order bit
of the byte address.
This pin is multiplexed between PCI, HPI, and EMIFA.
For EMIFA, this is the Bank Address 1 output EM_BA[1] (O/Z).
PCI_DEVSEL/
IPU When connected to a 16 bit asynchronous memory this pin is the lowest order bit
HCNTL1/ B3 I/O/Z
DV
DD33
of the 16-bit word address.
EM_BA[1]
When connected to an 8-bit asynchronous memory, this pin is the second bit of
the address.
This pin is multiplexed between PCI, ATA, GPIO, and EMIFA.
PCI_RSV2/INTRQ/ IPD
B10 I/O/Z In EMIFA mode, this pin is reserved.
GP[18]/EM_RSV0 DV
DD33
This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
PCI_RST/ This pin is multiplexed between PCI, ATA, GPIO, and EMIFA.
IPD
DA2/ C10 I/O/Z In EMIFA mode, this pin is address bit 22 output EM_A[22] (O/Z).
DV
DD33
GP[13]/EM_A[22] This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
This pin is multiplexed between PCI, ATA, GPIO, and EMIFA.
PCI_RSV0/DA1/ IPD
A9 I/O/Z In EMIFA mode, this pin is address bit 21 output EM_A[21] (O/Z).
GP[16]/EM_A[21] DV
DD33
This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
This pin is multiplexed between PCI ATA, GPIO, and EMIFA.
PCI_RSV1/DA0/ IPD
E9 I/O/Z In EMIFA mode, this pin is address bit 20 output EM_A[20] (O/Z).
GP[17]/EM_A[20] DV
DD33
This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
PCI_CBE1/ This pin is multiplexed between PCI, ATA, GPIO, and EMIFA.
IPU
ATA_CS1/ C2 I/O/Z In EMIFA mode, this pin is address bit 19 output EM_A[19] (O/Z).
DV
DD33
GP[32]/EM_A[19] This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
PCI_CBE0/ This pin is multiplexed between PCI, ATA, GPIO, and EMIFA.
IPU
ATA_CS0/ F4 I/O/Z In EMIFA mode, this pin is address bit 18 output EM_A[18] (O/Z).
DV
DD33
GP[33]/EM_A[18] This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
PCI_IRDY/ This pin is multiplexed between PCI, HPI, and EMIFA.
IPU
HRDY/ A3 I/O/Z In EMIFA mode, this pin is address bit 17 output EM_A[17] (O/Z).
DV
DD33
EM_A[17]/(CLE) When used for EMIFA (NAND), this pin is Command Latch Enable output (CLE).
PCI_TRDY/ This pin is multiplexed between PCI, HPI, and EMIFA.
IPU
HHWIL/ E6 I/O/Z For EMIFA, this pin is address bit 16 output EM_A[16] (O/Z).
DV
DD33
EM_A[16]/(ALE) When used for EMIFA (NAND), this pin is Address Latch Enable output (ALE).
PCI_AD31/ This pin is multiplexed between PCI, ATA, HPI, and EMIFA.
IPD
DD15/ A8 I/O/Z For EMIFA, this pin is address bit 15 output EM_A[15] (O/Z).
DV
DD33
HD31/EM_A[15] This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
PCI_AD30/ This pin is multiplexed between PCI, ATA, HPI, and EMIFA.
IPD
DD14/ C9 I/O/Z For EMIFA, this pin is address bit 14 output EM_A[14] (O/Z).
DV
DD33
HD30/EM_A[14] This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
PCI_AD29/ This pin is multiplexed between PCI, ATA, HPI, and EMIFA.
IPD
DD13/ B8 I/O/Z For EMIFA, this pin is address bit 13 output EM_A[13] (O/Z).
DV
DD33
HD29/EM_A[13] This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
PCI_AD28/ This pin is multiplexed between PCI, ATA, HPI, and EMIFA.
IPD
DD12/ D9 I/O/Z For EMIFA, this pin is address bit 12 output EM_A[12] (O/Z).
DV
DD33
HD28/EM_A[12] This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
PCI_AD27/ This pin is multiplexed between PCI, ATA, HPI, and EMIFA.
IPD
DD11/ A6 I/O/Z For EMIFA, this pin is address bit 11 output EM_A[11] (O/Z).
DV
DD33
HD27/EM_A[11] This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
PCI_AD26/ This pin is multiplexed between PCI, ATA, HPI, and EMIFA.
IPD
DD10/ C8 I/O/Z For EMIFA, this pin is address bit 10 output EM_A[10] (O/Z).
DV
DD33
HD26/EM_A[10] This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
PCI_AD25/ This pin is multiplexed between PCI, ATA, HPI, and EMIFA.
IPD
DD9/ B6 I/O/Z For EMIFA, this pin is address bit 9 output EM_A[9] (O/Z).
DV
DD33
HD25/EM_A[9] This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
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