Datasheet

TMS320DM6467T
SPRS605C –JULY 2009–REVISED JUNE 2012 www.ti.com
Table 7-148. JTAG ID Register Selection Bit Descriptions
BIT NAME DESCRIPTION
31:28 VARIANT Variant (4-Bit) value. DM6467T value: 0001 [Silicon Revision 3.0 and later].
27:12 PART NUMBER Part Number (16-Bit) value. DM6467T value: 1011 0111 0111 0000.
11-1 MANUFACTURER Manufacturer (11-Bit) value. DM6467T value: 0000 0010 111.
0 LSB LSB. This bit is read as a "1" for DM6467T.
7.29.2 JTAG Test-Port Electrical Data/Timing
Table 7-149. Timing Requirements for JTAG Test Port
(1) (2)
(see Figure 7-96)
-1G
NO. UNIT
MIN MAX
1 t
c(TCK)
Cycle time, TCK 20 ns
2 t
w(TCKH)
Pulse duration, TCK high 0.4T ns
3 t
w(TCKL)
Pulse duration, TCK low 0.4T ns
4 t
c(RTCK)
Cycle time, RTCK 20 ns
5 t
w(RTCKH)
Pulse duration, RTCK high 0.4R ns
6 t
w(RTCKL)
Pulse duration, RTCK low 0.4R ns
7 t
su(TDIV-RTCKH)
Setup time, TDI/TMS/TRST valid before RTCK high 12 ns
8 t
h(RTCKH-TDIV)
Hold time, TDI/TMS/TRST valid after RTCK high 0 ns
9 t
su(EMUV-TCKH)
Setup time, EMU[1:0] valid before TCK high 1.5 ns
10 t
h(TCKH-EMUV)
Hold time, EMU[1:0] valid after TCK high 4 ns
(1) T = TCK cycle time in ns. For example, when TCK frequency is 20 MHz, use T = 50 ns.
(2) R = RTCLK cycle time in ns. For example, when RTCK frequency is 20 MHz, use T = 50 ns.
Table 7-150. Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port
(1)
(see Figure 7-96)
-1G
NO. PARAMETER UNIT
MIN MAX
11 t
d(RTCKL-TDOV)
Delay time, RTCK low to TDO valid -1 8 ns
12 t
d(TCKH-EMUV)
Delay time, TCK high to EMU[1:0] valid 2.5 T - 2.5 ns
(1) T = TCK cycle time in ns. For example, when TCK frequency is 20 MHz, use T = 50 ns.
346 Peripheral Information and Electrical Specifications Copyright © 2009–2012, Texas Instruments Incorporated
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