Datasheet

TMS320DM6467T
SPRS605C –JULY 2009–REVISED JUNE 2012 www.ti.com
Table 3-9. Asynchronous External Memory Interface (EMIFA) Terminal Functions
SIGNAL
TYPE
(1)
OTHER
(2) (3)
DESCRIPTION
NAME NO.
EMIFA BOOT CONFIGURATION
EMIFA CS2 space data bus width. This pin is multiplexed between EMIFA control
and the VPIF. At reset, the input state is sampled to set the EMIFA data bus
width for the CS2 (boot) chip select region.
VP_DOUT4/ IPD
AA7 I/O/Z
CS2BW DV
DD33
For an 8-bit-wide EMIFA data bus, CS2BW = 0.
For a 16-bit-wide EMIFA data bus, CS2BW = 1.
After reset, this pin is video port data output 4 (VP_DOUT4).
DSP boot source bit. This pin is multiplexed between DSP boot and the VPIF. At
reset, the input state is sampled to set the DSP boot source DSPBOOT.
VP_DOUT6/ IPD
AC5 I/O/Z The DSP is booted by the ARM when DSPBOOT = 0.
DSPBOOT DV
DD33
The DSP boots from EMIFA when DSPBOOT=1.
After reset, this pin is video port data output 6 (VP_DOUT6).
EMIFA FUNCTIONAL PINS: ASYNC
This pin is multiplexed between PCI, HPI, and EMIFA.
PCI_CBE2/
IPU In EMIFA mode, this pin is Chip Select 2 output EM_CS2 (O/Z). This is the chip
HDS2/ C4 I/O/Z
DV
DD33
select used for EMIFA boot modes. Asynchronous memories (i.e., NOR Flash) or
EM_CS2
NAND flash.
PCI_CBE3/ This pin is multiplexed between PCI, HPI, and EMIFA.
IPU
HR/W A5 I/O/Z In EMIFA mode, this pin is Chip Select 3 output EM_CS3 (O/Z). Asynchronous
DV
DD33
EM_CS3 memories (i.e., NOR Flash).
This pin is multiplexed between PCI, ATA, GPIO, and EMIFA.
PCI_GNT/
IPU In EMIFA mode, this pin is Chip Select 4 output EM_CS4 (O/Z). Asynchronous
DACK/ D10 I/O/Z
DV
DD33
memories (i.e., NOR Flash).
GP[12]/ EM_CS4
This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
PCI_REQ/ This pin is multiplexed between PCI, ATA, GPIO, and EMIFA.
IPU
DMARQ/ B9 I/O/Z In EMIFA mode, this pin is Chip Select 5 output EM_CS5 (O/Z).
DV
DD33
GP[11]/ EM_CS5 This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
PCI_IDSEL/
IPU This pin is multiplexed between PCI, ATA, and EMIFA.
HDDIR/ E8 I/O/Z
DV
DD33
In EMIFA mode, this pin is the read/write output EM_R/W (O/Z).
EM_R/W
PCI_SERR/
IPU This pin is multiplexed between PCI, HPI, and EMIFA.
HDS1/ B2 I/O/Z
DV
DD33
In EMIFA mode, this pin is the output enable output EM_OE (O/Z).
EM_OE
PCI_STOP/
IPU This pin is multiplexed between PCI, HPI, and EMIFA.
HCNTL0/ D5 I/O/Z
DV
DD33
In EMIFA mode, this pin is the write enable output EM_WE (O/Z).
EM_WE
PCI_PERR/
IPU
HCS/ C3 I/O/Z
DV
DD33
EM_DQM1
These pins are multiplexed between PCI, HPI, and EMIFA.
In EMIFA mode, these pins are EM_DQM[1:0] and act as byte enables (O/Z).
PCI_PAR/
IPU
HAS/ D4 I/O/Z
DV
DD33
EM_DQM0
PCI_INTA/ This pin is multiplexed between PCI and EMIFA.
IPU
EM_WAIT2/ C11 I/O/Z In EMIFA mode, this pin is wait state extension input 2 EM_WAIT2 (I).
DV
DD33
(RDY2/BSY2) When used for EMIFA (NAND), this pin is the ready/busy 2 input (RDY2/BSY2).
PCI_RSV5/IORDY/ This pin is multiplexed between PCI, ATA, GPIO, and EMIFA.
IPU
GP[21]/EM_WAIT3/ D11 I/O/Z In EMIFA mode, this pin is wait state extension input 3 EM_WAIT3 (I).
DV
DD33
(RDY3/BSY3) When used for EMIFA (NAND), this pin is the ready/busy 3 input (RDY3/BSY3).
PCI_RSV4/DIOW/ This pin is multiplexed between PCI, ATA, GPIO, and EMIFA.
IPU
GP[20]/EM_WAIT4/ A11 I/O/Z In EMIFA mode, this pin is wait state extension input 4 EM_WAIT4 (I).
DV
DD33
(RDY4/BSY4) When used for EMIFA (NAND), this pin is the ready/busy 4 input (RDY4/BSY4).
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 4.8.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
34 Device Overview Copyright © 2009–2012, Texas Instruments Incorporated
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